Sharif Digital Repository

The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

We propose a no-go theorem by proving the impossibility of constructing a deterministic quantum circuit that iterates a unitary oracle by calling it only once. Different schemes are provided to bypass this result and to approximately realize the iteration. The optimal scheme is also studied. An interesting observation is that for a large number of iterations, a trivial strategy like using the identity channel has the optimal performance, and preprocessing, postprocessing, or using resources like entanglement does not help at all. Intriguingly, the number of iterations, when being large enough, does not affect the performance of the proposed schemes  

Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,... 

It is shown that negative capacitance (NC) circuits can be systematically used to improve the gain-bandwidth product of the operational amplifiers (opamps). The NC circuit moves the nondominant pole of the opamp to higher frequency by decreasing the parasitic capacitance of the critical node. The impedance at the input of the NC circuits is neither purely capacitive nor negative at all frequencies. A design guide is presented by deriving the circuit model for a conventional NC circuit and investigating the extent of the improvement that can be achieved in a circuit by the use of the NC circuit. The model is then used to present the design guide for widebanding the multistage opamps with... 

This study proposes a new fault detection method for modular multilevel converter (MMC) semiconductor power switches. While in common MMCs, the cells capacitor voltages are measured directly for control purposes, in this study voltage measurement point changes to the cell output terminal improving fault diagnosis ability. Based on this measurement reconfiguration, a novel fault detection algorithm is designed for MMCs semiconductor power switches. The open circuit and short circuit faults are detected based on unconformity between modules output voltage and switching signals. Simulation and experimental results confirm accurate and fast operation of the proposed method in faulty cell... 

When illuminated by TM polarized waves, periodic arrays of graphene ribbons are known to exhibit plasmonic resonances due to their dual inductive-capacitive nature. It is demonstrated here that even in TE polarization, resonances can be observed in these structure. These resonances, which are of nonplasmonic origin, are explained by means of a circuit model. It is shown that, for a certain frequency range, arrays of graphene ribbons have both capacitive and inductive properties, which lead to an ultra-sharp inductor-capacitor resonance. The banw idth of this resonance can be as narrow as ∼0.0002 nm at a wavelength of 630 nm. The resonance can also be viewed as the grating excitation of a TE... 

While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gated cores are referred to as Dark Silicon. At the same time, growing reliability issues due to process variations and soft errors challenge the cost-effective deployment of future technology nodes. This paper presents a reliability management system for Dark Silicon chips (dsReliM) that optimizes for reliability of on-chip systems while jointly accounting for soft errors, process variations and the thermal design power (TDP) constraint. Towards the TDP-constrained reliability optimization, dsReliM... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

Generous flexibility of Look-Up Tables (LUTs) in implementing arbitrary functions comes with significant performance and area overheads compared with their Application-Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this paper, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics (HL). Since higher input functions have diverse classes, we leverage Shannon decomposition to break them into smaller ones to either reduce the HL design space complexity... 

Disk traces are typically used to analyze real-life workloads and for replay-based evaluations. This approach benefits from capturing important details such as varying behavior patterns, bursty activity, and diurnal patterns of system activity, which are often missing from the behavior of workload synthesis tools. However, accurate capture of such details requires recording traces containing long durations of system activity, which are difficult to use for replay-based evaluation. One way of solving the problem of long storage trace duration is the use of disk simulators. While publicly available disk simulators can greatly accelerate experiments, they have not kept up with technological... 

An ultra-broadband absorber of light is proposed by using periodic array of ultra-thin metallic ribbons on top of a lossless quarter-wavelength dielectric spacer placed on a metallic reflector. We propose a fully analytical circuit model for the structure, and then the absorber is duly designed based on the impedance matching concept. As a result, normalized bandwidth of 99.5% is realized by the proposed absorbing structure in mid-infrared regime. Performing a numerical optimization algorithm, we could also reach to normalized bandwidth of 103%  

This article presents an analytical solution for power output from a doubly curved piezoelectric energy harvester. The energy harvester is made of an elastic core layer coupled with one or two surface-bonded piezoelectric layers. Five mechanical equations of motion together with Gauss's equation are derived on the basis of first-order shell theory and solved simultaneously for simply supported mechanical boundary conditions. The influence of structural damping is taken into account using Rayleigh damping. The electromechanical frequency response functions that relate the power output and circuit load resistance are identified from the exact solutions. Finally, the performance of the system... 

The effects of resonator topology on the phase noise of LC oscillators are studied in this paper. It is shown that there is a neglected factor that can considerably influence the phase noise behavior of the oscillator. We designate this factor as the Inductance Energy Factor (IEF), which directly depends on the topology of the resonator. It is shown that through proper design of the resonator for a better IEF, the oscillator phase noise can be improved. It is also shown that by modifying the resonator structure to improve IEF, the phase noise does not have to be constrained by the minimum realizable inductance and its maximum quality factor. Therefore, the power-phase noise trade-off remains... 

Wireless Nano-scale Sensor Networks (WNSNs) are very simple and energy restricted networks that operate over terahertz band ranging from 0.1-10 THz, which faces significant molecular absorption noise and attenuation. Given these challenges, reliability, energy efficiency, and simplicity constitute the main criteria in designing communication protocols for WNSNs. Due to its simplicity and energy efficiency, carrier-less pulse based modulation is considered the best candidate for WNSNs. In this paper, we compare the performance of four different carrier-less modulations, PAM, OOK, PPM, and BPSK, in the context of WNSNs operating within the terahertz band. Our study shows that although BPSK is... 

The ever increasing density and performance of FPGAS, has increased the importance and popularity of soft processors. The growing gap between the speed of processors and memories can partly be compensated through memory hierarchy. Since memory accesses follow a non-uniform distribution, and vary from one application to another, variable set-associative cache architectures have emerged. In this paper, a novel cache architecture, primarily aimed at soft processors, is proposed to address the variable access demands of applications, through dynamically configurable line-associativity, with no memory overhead. The FPGA implementation of the proposed architecture achieves an average miss count... 

Nowadays, manufacturing enterprises have been faced with a globalized competitive environment. In this fierce condition, Cloud Manufacturing paradigm emerged as a promising concept for competition. It provides effective solutions and tools for manufacturing enterprises to collaborate in globalized market. The revolution that Cloud Manufacturing has created is based on the redefinition of the classic methods to those which are appropriate for todays' modern and globalized manufacturing environments. In parallel with cloud-based revolution, the expansion of internet-based technologies has been started. These technologies previously have been applied in many fields and resulted in... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the...