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An Effective Power Gating Method for NoC through Idle Time Management

Farrokhbakht, Hossein | 2017

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 49694 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hesabi, Shahin
  7. Abstract:
  8. With the advent in technology and shrinking the transistor size down to nano scale, static power may become the dominant power component in Networks-on-Chip (NoCs). Power-gating is an efficient technique to reduce the static power of under-utilized resources in different types of circuits. For NoC, routers are promising candidates for power gating, since they present high idle time. However, routers in a NoC are not usually idle for long consecutive cycles due to distribution of resources in NoC and its communication-based nature, even in low network utilizations. Therefore, power-gating loses its efficiency due to performance and power overheads of the packets that encounter powered-off routers. we propose Turn-on on Turn (TooT) and NAFIS, which reduce the number of wake-ups by leveraging the characteristics of deterministic routing algorithms and mesh topology. TooT avoids powering a router on when it forwards a straight packet or ejects a packet, i.e., a router is powered on only when either a packet turns through it or its associated node injects a packet. NAFIS also avoids powering a router on when it injects a packet and tries to hide wake-up latency. Experimental results on PARSEC benchmarks demonstrate that, compared with the conventional power-gating, the proposed method improves static power and performance by 57.9% and 35.3%, respectively, at the cost of a negligible area overhead
  9. Keywords:
  10. Idle Time ; Energy Consumption ; Power Gating ; Network-on-Chip (NOC) ; Power Reduction

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