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Improving Reliability of STT-MRAM Caches against Read Disturbance Errors

Aliagha, Ensieh | 2017

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 50210 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Miremadi, Ghasem
  7. Abstract:
  8. On-chip caches are regarded as a solution for increasing performance gap between main memory and CPU. In recent years, with the development in the performance of processing cores, the demands for larger on-chip caches are also increased. With the technology scaling trend, SRAM-based on-chip caches suffer from limited scalability, high leakage power consumption and vulnerability to soft errors. Among emerging non-volatile memories, STT-MRAMs are the most promising alternative for SRAMs in large last-level on-chip caches due to their higher density and near zero leakage power. However, the reliability of STT-MRAMs is threatened by soft and hard errors. Soft errors in STT-MRAMs can be categorized as follows: read disturbance, write failure, retention failure and false reads. With further technology scaling, the read current does not scale down as much as the write current. Therefore, the amount of read and write currents becomes closer to each others and the read disturbance probability increases. Previous studies that addressed the read disturbance restore the block contents after each read operation, which leads to increase in the write failure rate. Both read disturbance and write failure, which cause a soft error in the cache cells, have an asymmetric behaviour. Read disturbance occurs only in STT-MRAM cells storing '1' value, and write failure error rate in a '0'→'1' transition is much higher than that in a '1'→'0' transition. In this study, we propose REACT, a Read/write Error rate Aware Coding Technique to improve the reliability of the emerging STT-MRAM caches. REACT decreases the read disturbance and write failure rates by reducing the total number of '1's and the overall '0'→'1' transitions on a cache block update. Our simulation results show, on average, REACT improves the reliability of last-level STT-MRAM caches against read disturbances and write failures by about 17.4% and 17.9%, respectively. The cache energy consumption is also reduced by 2.2%, on average. These improvements are achieved by imposing negligible area and performance overheads (less than 1%)
  9. Keywords:
  10. Static Random Access Memory (SRAM)Cell ; Spin Transfer Torque-Magnetic (STT-MRAM) ; Write Error ; Coding ; On-Chip Memories ; Read Disturbance

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