Sharif Digital Repository

Embedded SRAM unit is recognized as an important block in the systems on chip. In recent years due to an abrupt increase in the number of such systems which often work with battery, the priority of designing of low power circuits has been increased. Furthermore, increase in the number of transistors in the SRAM and increase in leakage current of MOS transistors with technology scaling have rendered the SRAM into the main energy consumer (from both static and dynamic view).In the writing operation due to the full swing of bit line, the dynamic power forms the main chunk of the consumptive power. The static consumptive power mostly happens due to the leakage current of broken cells in an array... 

A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. This reinforces the need to design a more compact SRAM. With the increase in the processors speed, memories speed needs to be increased to enhance the overall throughput. Current Sense Amplifiers have partially solved the problem. However the area occupied by these amplifiers is still a large amount. The input offset is also not negligible. Due to their cascode configuration, these circuits cannot be scaled with the voltage scaling. In this thesis we proposed a new hybrid sense amplifier with an added phase, so the input offset can be cancelled with a large... 

Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of... 

Reconfigurable devices are a popular platform for fast prototyping of digital system due to having high performance of hardware implementation along with flexibility of software. However, reconfigurable devices suffer from area, performance and dependability gaps in comparison with their Application Specific Integrated Circuit (ASIC) counterparts, which greatly limits their application.
The dependability gap originates from the sensitivty of configuration memory to soft errors. When a reconfigurable device configuration memory is affected by soft errors, their configuration will be invalid until reconfigured. Since the routing fabric is the origion of over 80% of soft errors in... 

The explosive growth of battery operated devices has made low-power design a priority in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The increasing number of transistor count in the SRAM units and the surging leakage current of the MOS transistors in the scaled technologies have made the SRAM unit a power hungry block from both dynamic and static perspectives. One of the key strategies for reducing power consumption is reducing the supply voltage to near or below the threshold voltage of the transistor. However, as supply voltage decreases to tackle the power consumption, the data stability of the SRAM cells have become a major concern in recent... 

Embedded systems play an important role in many applications in various areas of human life. A large group of these systems are portable devices that have limited energy budget and therefore require considering the energy consumption in their design. Today, memories are responsible for a considerable portion of energy consumption in embedded systems, mainly because of their static leakage power consumption. Memories used in embedded systems are usually based on either SRAM (mostly used on-chip as cache or scratchpad memory) or DRAM (mostly used off-chip as main memory). The high leakage power of these memories (especially SRAM) is not negligible and hence has persuaded researchers to find... 

SRAM has a very wide application in different platforms including Cache Memory in Microcontrollers, etc. also SRAM is the first candidate for memory usage in every application needing High speed or static memory circuits. SRAM Cells are constructed by Minimum size transistors in each technology node and usually the newest technology nodes are used for building SRAM blocks for accommodating maximum number of SRAM Cells in a specific area. Going through smaller technology nodes, Leakage current and Process variations problem, creates serious difficulties in designing Low Power or High speed SRAM Memories and many academic and industrial works are done wishing for improvement in SRAM power... 

Vulnerability of SRAM-based FPGAs to soft errors signals the importance of applying fault-tolerant methods in FPGAs used in safety-critical applications. Previous methods to protect SRAM-based FPGAs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to Single Event-Multiple Upsets (SEMU). This thesis presents a Highly Available Fault-Tolerant Architecture (HAFTA) to protect SRAM-based FPGA designs against SEMUs in both configuration and user bits. In HAFTA, the entire design is duplicated and the main and replica flip-flops are compared at each clock cycle to detect any possible mismatch. To save the latest correct state of the... 

From the cache of the personal computers to the main memory unit of SOCs, medical and wearable chips, Static Random Access Memory (SRAM) is widely utilizes. Preferable performance for SRAM varies with regard to the operating field. For instance, high speed access and performance is emphasized in the design of the cache for PCs. In contrast, power consumption and the area of the memory are the key design considerations for SOCs. Hence, the field in which SRAM is used, should be thoroughly studied. SOCs and medical chips suffer limitations in design due to using batteries as the source of energy and SRAMs consume a significant part of total power and occupy a large area on these chips. One of... 

In recent years, emerging Non-Volatile Memories (NVMs) have become promising alternatives for existing memory technologies. Due to shortcomings of SRAM memory in nanometer era,NVMs such as Phase-Change Memory (PCM) can be used in configuration memories of Field-Programmable Gate Arrays (FPGAs). Despite prominent features of emerging NVMs, they suffer from high write-power, high write-latency, and limited number of reliable write opera-tions. In addition, a dedicated Peripheral Circuit (PC) which is required to convert the NVM state to the equivalent voltage level can impose significant area and power overheads to FPGAs.In this thesis, a reliable power-efficient hybrid architecture employing... 

With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. The soft errors vulnerability of SRAM-based FPGAs limits their usage in safety-critical applications. Moreover, the rate of multiple soft errors increases due to the feature size reduction. Hence, this issue becomes a challenge against reliability of the implemented circuit on SRAM-based FPGAs. Appealing to specifics such as low cost and re-configurability in SRAM based FPGAs provide this ability to change implemented design remotely. This advantage is not negligible in safety critical... 

Bias Temperature Instability (BTI) is known as one serious reliability concern in nanoscale technology sizes. BTI gradually degrades threshold voltage (Vth) of MOS transistors. The main consequence of Vth degradation in SRAM cell transistors is the Static Noise Margin (SNM) degradation that makes SRAM cells susceptible against soft errors. SNM degradation in SRAM cells results in bit-flip occurrences and should be monitored accurately before resulting in permanent failures. This work proposes a sensor called Current-based BTI Sensor (CBS) to assess the aging state of SRAM cells. CBS measures BTI-induced SNM degradation of SRAM cells by monitoring the write current shifts due to BTI. The... 

Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most affected modules by NBTI. Variations in duty Cycles and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and distributes... 

A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. The fast growth of battery-operated portable applications has compelled the SRAM designers to consider subthreshold operation as a viable choice to reduce the power consumption. In most such applications, the speed of the SRAM is not the challenging parameter therefore the thrust toward low power design influence the design choices in various parts of the SRAM architecture. With technology scaling to the nanometer, Bitline leakage current and offset voltage deteriorate SRAM reading performance since SRAM cell current is close to the Bitline leakage current.... 

On-chip caches are regarded as a solution for increasing performance gap between main memory and CPU. In recent years, with the development in the performance of processing cores, the demands for larger on-chip caches are also increased. With the technology scaling trend, SRAM-based on-chip caches suffer from limited scalability, high leakage power consumption and vulnerability to soft errors. Among emerging non-volatile memories, STT-MRAMs are the most promising alternative for SRAMs in large last-level on-chip caches due to their higher density and near zero leakage power. However, the reliability of STT-MRAMs is threatened by soft and hard errors. Soft errors in STT-MRAMs can be... 

By scaling the technology node, leakage power and process variations emerge as the two important factors to design a chip. Static power becomes more important when the number of portable devices which spend most of the time in the idle mode is increasing.Process variations lessen performance, reliability and lead to more leakage power. To mitigate these limitations multiple devices have been proposed to displace Bulk MOSFET.Among these devices we can name FinFET and CNTFET transistors. FinFET transistors due to their superior gate control in compare to Bulk MOSFETs transistor have shown lesser short channel effects, more scalability, more I_on to I_off ratio and lesser process variations.... 

Signifcant downscaling of CMOS technology to provide high performance along with low power consumption has been accompanied by reliability degradations such as increased noise sensitivity and reliability concern due to aging phenomena (transient and permanent failuers). In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, but also it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom... 

Reliability, performance, and energy consumption are among the most important constraints that should be satisfied in modern processors design. More than 60% of the chip area is occupied by on-chip SRAM memories and they not only contribute in a large fraction of energy consumption, but also are the most error-prone components. Radiation-induced soft errors in on-chip memories are a major concern in modern processors design. Although Single Event Upsets (SEUs) have been known to be the main concern regarding SRAM memory reliability over the past decades, with the continued downscaling of technology, the occurrence rate of Multiple-Bit Upsets (MBUs) is comparable to that of SEUs in today’s... 

With the technology scaling trend in recent years, leakage power has become a major challenge for SRAM-based on-chip memories. According to the recent reports, SRAM-based on-chip memories contribute to more than half of the processors’ power consumption. Accordingly, in recent years, researchers have tried to find an alternative technology for SRAMs in on-chip memories. The International Technology Roadmap for Semiconductors (ITRS) recently announced that STT-MRAMs are the most promising technology to replace SRAMs. While STT-MRAMs benefit from low energy consumption, high endurance, and high density compared to other non-volatile memory technologies, comparing with SRAMs, STT-MRAMs have...