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A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era

Seifoori, Z ; Sharif University of Technology | 2017

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  1. Type of Document: Article
  2. DOI: 10.23919/DATE.2017.7927201
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2017
  4. Abstract:
  5. Continuous down scaling of CMOS technology in recent years has resulted in exponential increase in static power consumption which acts as a power wall for further transistor integration. One promising approach to throttle the substantial static power of Field-Programmable Gate Array (FPGAs) is to power off unused routing resources such as switch boxes, known as dark silicon. In this paper, we present a Power gating Switch Box Architecture (PESA) for routing network of SRAM-based FPGAs to overcome the obstacle for further device integration. In the proposed architecture, by exploring various patterns of used multiplexers in switch boxes, we employ a configurable controller to turn off unused resources in the routing network. Our study shows that due to the significant percentage of unused switches in the routing network, PESA is able to considerably improve power efficiency in SRAM-based FPGAs. Experimental results carried out on different benchmarks using VPR toolset show that PESA decreases power consumption of the routing network up to 75% as compared to the conventional architectures while preserving the performance intact. © 2017 IEEE
  6. Keywords:
  7. Benchmarking ; Electric power utilization ; Field programmable gate arrays (FPGA) ; Network architecture ; Device integration ; Exponential increase ; Power efficiency ; Power gating switches ; Proposed architectures ; Routing networks ; Routing resources ; Static power consumption ; Network routing
  8. Source: 20th Design, Automation and Test in Europe, DATE 2017, 27 March 2017 through 31 March 2017 ; 2017 , Pages 1342-1347 ; 9783981537093 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/7927201