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AWARE: Adaptive way allocation for reconfigurable ECCs to protect write errors in STT-RAM caches

Azad, Z ; Sharif University of Technology | 2017

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  1. Type of Document: Article
  2. DOI: 10.1109/TETC.2017.2701880
  3. Publisher: IEEE Computer Society , 2017
  4. Abstract:
  5. Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To this end, instead of protecting all cache lines using strong ECCs, AWARE employs a simple ECC that guarantees a given reliability level for the majority of writes. Meanwhile, when a data block with high error rate is written, one way in the target set is adaptively configured to store the check bits of a strong ECC for this block. The evaluation results show that, compared with conventional ECCs, AWARE reduces the ECC area by about 81.2% and the cache energy consumption by about 9.5%. These reductions are achieved by imposing less than 1% performance overhead and without compromising the reliability. IEEE
  6. Keywords:
  7. Asymmetric switching ; Error analysis ; Reconfigurable Error-Correcting Codes (ECCs) ; STT-RAM caches ; Thermal stability ; Write error ; Cache memory ; Codes (symbols) ; Cost reduction ; Energy utilization ; Error correction ; Errors ; Program processors ; Reliability ; Static random access storage ; Stochastic systems ; Switches ; Thermodynamic stability ; Error correcting code ; Error correction codes ; Magnetic tunneling ; Random access memory ; Stt rams ; Random access storage
  8. Source: IEEE Transactions on Emerging Topics in Computing ; 2017 ; 21686750 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/7921585