Loading...

A Hardware-Software Partitioner for Deep Learning Algorithms

Haghighi, Sepand | 2019

385 Viewed
  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 52665 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Hessabi, Shahin
  7. Abstract:
  8. Deep learning, as a subdivision of machine learning, attempts to model high-level concepts by using a deep graph, consisting of several layers of linear and nonlinear transformations. Implementing these algorithms on hardware is a big challenge.¬This project offers a system in which various hardware methodologies can be used to implement deep learning algorithms side by side. The overall structure of the system consists of high-level programming interfaces for implementation and expression of machine learning algorithms by the user, which will be available as libraries in a high-level programming language such as Python, Ruby, and Julia. These interfaces allow the user to evaluate their algorithms on different machines without changing the code, regardless of the limitations of the implementation methods. The main purpose of the design of this hardware-software interface is to provide the conditions for using graphical processing unit, central processing unit and field programmable gate array in a single structure so that each of them can be used to better process deep learning algorithms. The system will also be able to intelligently separate and distribute computational load on various hardware available on the system, depending on the features of each segment
  9. Keywords:
  10. Field Programmable Gate Array (FPGA) ; Deep Learning ; Classification ; Graphics Procssing Unit (GPU) ; Hardware-Software Interface

 Digital Object List

 Bookmark

No TOC