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Toward on-chip network security using runtime isolation mapping

Bayat Sarmadi, M ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1145/3337770
  3. Publisher: Association for Computing Machinery , 2019
  4. Abstract:
  5. Many-cores execute a large number of diverse applications concurrently. Inter-Application interference can lead to a security threat as timing channel attack in the on-chip network. A non-interference communication in the shared on-chip network is a dominant necessity for secure many-core platforms to leverage the concepts of the cloud and embedded system-on-chip. The current non-interference techniques are limited to static scheduling and need router modification at micro-Architecture level. Mapping of applications can effectively determine the interference among applications in on-chip network. In this work, we explore non-interference approaches through run-Time mapping at software and application level.We map the same group of applications in isolated domain(s) to meet non-interference flows. Through run-Time mapping, we can maximize utilization of the system without leaking information. The proposed run-Time mapping policy requires no router modification in contrast to the best known competing schemes, and the performance degradation is, on average, 16% compared to the state-of-The-Art baselines. © 2019 Copyright held by the owner/author(s)
  6. Keywords:
  7. Non-interference ; On-chip interconnect ; Runtime mapping ; Timing side-channel ; Application programs ; Computer architecture ; Mapping ; System-on-chip ; Diverse applications ; Micro architectures ; Non interference ; On chip interconnect ; Performance degradation ; Run-time mapping ; Static scheduling ; Timing side channels ; Network security
  8. Source: ACM Transactions on Architecture and Code Optimization ; Volume 16, Issue 3 , 2019 ; 15443566 (ISSN)
  9. URL: https://dl.acm.org/doi/10.1145/3337770