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Synchronization-Phase Alignment of All-Digital Phase-Locked Loop Chips for a 60-GHz MIMO Transmitter and Evaluation of Phase Noise Effects

Salarpour, M ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TMTT.2019.2910060
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57-63-GHz multiple-input multiple-output (MIMO) transmitter (TX) with a digital beam-steering capability. The ADPLL TX chains are first fabricated in nanoscale CMOS and then time-synchronized and frequency-phase locked by a field-programmable gate array (FPGA) evaluation board. The calibration approach for phase alignment is carried out using a cancellation method to acquire the out-of-phase state within two ADPLLs. The accuracy of beam steering and phase alignment is investigated and analyzed based on a time-domain model for ADPLL to consider the impact of phase noise. The analysis results offer the required values of the ADPLL parameters to allow a millimeter-wave (mm-wave) MIMO TX with a highly accurate digital beam-steering capability
  6. Keywords:
  7. 60-GHz multiple-input multiple-output (MIMO) ; All-digital phase-locked loop (ADPLL) ; Cancellation method ; Digital beam steering ; Highly accurate beam steering ; Phase-alignment accuracy ; Alignment ; Beamforming ; Codes (symbols) ; Feedback control ; Field programmable gate arrays (FPGA) ; Locks (fasteners) ; Millimeter waves ; Phase locked loops ; Phase noise ; Telecommunication repeaters ; Time domain analysis ; Transmitters ; All digital phase locked loop ; Beam-steering ; Phase alignment ; Phase coherence ; MIMO systems
  8. Source: IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 7 , 2019 , Pages 3187-3199 ; 00189480 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8718820