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A 125-ps 8-18-GHz CMOS integrated delay circuit

Ghazizadeh, M. H ; Sharif University of Technology | 2019

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  1. Type of Document: Article
  2. DOI: 10.1109/TMTT.2018.2880766
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2019
  4. Abstract:
  5. A wideband integrated delay chain chip with 5-bit main delay control, two error correction bits, maximum delay of 125-and 3.9-ps delay resolution, designed and fabricated in a 0.18-μ m CMOS technology is presented. This delay chain is a cascade of seven passive internal-switched delay blocks which the five main bits are based on novel delay structures. The proposed delay structures are similar to second-, fourth-, and sixth-order all-pass networks and are robust to mismatch effects of resistive parasitics of transistor switches. Measurement results of the fabricated delay chain show 15.2-23.3-dB insertion loss and less than 3.3-ps rms delay error over the intended frequency band from 8-18 GHz. Input and output reflection coefficients are better than-11 dB for the delay chain including the effect of RF bondwires and pads. The fabricated chip occupies an area of 2.0 × 1.0 mm2 and has no dc power consumption. © 1963-2012 IEEE
  6. Keywords:
  7. All-pass network (APN) ; CMOS ; Delay chain ; Capacitance ; CMOS integrated circuits ; Electric impedance ; Error correction ; Insertion losses ; Switches ; Timing circuits ; Topology ; Transistors ; Allpass networks ; DC power consumption ; Delay chains ; Delays ; Fabricated chips ; Input and outputs ; Mismatch effects ; Transistor switch ; Delay circuits
  8. Source: IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 1 , 2019 , Pages 162-173 ; 00189480 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/8550707