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Total 146 records

    A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 1- 5 June , 2014 , pp. 1147-1150 ; ISSN: 02714310 Esmaeelzadeh, H ; Sharifkhani, M ; Shabany, M ; Sharif University of Technology
    Abstract
    This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW  

    An 8-bit 300MS/S switched-current pipeline ADC in 0.18μm CMOS

    , Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 1481-1484 ; 02714310 (ISSN) Sedighi, B ; Sharif Bakhtiar, M ; Sharif University of Technology
    2007
    Abstract
    In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply. © 2007 IEEE  

    An 8-bit current-mode folding ADC with optimized active averaging network

    , Article Scientia Iranica ; Volume 15, Issue 2 , 2008 , Pages 151-159 ; 10263098 (ISSN) Azin, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    Sharif University of Technology  2008
    Abstract
    In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008  

    On the importance of the number of fanouts to prevent the glitches in DPA-resistant devices

    , Article 13th International Computer Society of Iran Computer Conference on Advances in Computer Science and Engineering, CSICC 2008, Kish Island, 9 March 2008 through 11 March 2008 ; Volume 6 CCIS , 2008 , Pages 661-670 ; 18650929 (ISSN); 3540899847 (ISBN); 9783540899846 (ISBN) Moradi, A ; Salmasizadeh, M ; Manzuri Shalmani, M. T ; Sharif University of Technology
    2008
    Abstract
    During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable... 

    A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer

    , Article APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30 November 2008 through 3 December 2008 ; 2008 , Pages 1383-1386 ; 9781424423422 (ISBN) Saeedi, S ; Atarodi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    2008
    Abstract
    A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE  

    A high-speed and low-power voltage controlled oscillator in 0.18-μm CMOS process

    , Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 933-936 ; 02714310 (ISSN) Savadi Oskooei, M ; Afzali Kusha, A ; Atarodi, S. M ; Sharif University of Technology
    2007
    Abstract
    In this paper, we propose a new voltage controlled oscillator (VCO) with a high oscillation frequency yet low power consumption. The oscillator which is a single stage circuit has a low phase noise due to reduced noise sources. To evaluate the performance parameters, the oscillator was simulated in a 0.18-μm standard CMOS process. The results show that the oscillation frequency of VCO may vary between 4.66-5.9 GHz. Also, the phase noise of the VCO at oscillation frequency of 5.6 GHz is -99.7 dBc at 1 MHz offset frequency. Also, the power consumption was 4.8 mW at the same oscillation frequency. © 2007 IEEE  

    A low voltage, high speed, high resolution class AB switched current sample and hold

    , Article ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 1039-1042 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN) Rajaee, O ; Jahanian, A ; Sharif Bakhtiar, M ; Sharif University of Technology
    2006
    Abstract
    A high speed, high resolution switched-current sample and hold (SI S/H) based on a new class AB transconductance stage is presented. Simulations performed on the SI S/H in standard 0.18um CMOS technology with 1.5v supply voltage indicate low power dissipation, high sampling speed and high SNR. © 2006 IEEE  

    A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system

    , Article ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 3810-3813 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN) Adrang, H ; Lotfi, R ; Mafinejhad, K ; Tajalli, A ; Mehrmanesh, S ; Sharif University of Technology
    2006
    Abstract
    In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18μm CMOS process show a THD of less than 44dB for 0.6Vpp input signal and an input-referred noise of less than 45 nV/√Hz in worst case. The current consumption of each OTA is 1.5-mA. © 2006 IEEE  

    Design and Simulation of CMOS Based Magnetic Sensor for Biosensing Applications

    , M.Sc. Thesis Sharif University of Technology Mafi, Alireza (Author) ; Akbari, Mahmood (Supervisor) ; Fotowat-Ahmady, Ali (Supervisor)
    Abstract
    This paper presents a scalable and ultrasensitive magnetic biosensing scheme based on on-chip LC resonance frequency-shifting. The sensor transducer gain is demonstrated as being location-dependent on the sensing surface and proportional to the local polarization magnetic field strength |B|2 generated by the sensing inductor. To improve the gain uniformity, a periodic coil is proposed as a substitution for the standard process coil. As an implementation example, the circuit is designed in a 65nm CMOS process. The spatially uniform sensor gain of the array is verified by COMSOL simulations. Overall, the presented sensor demonstrates an improvement in the uniformity of the inductor’s magnetic... 

    A tunable high-Q active inductor with a feed forward noise reduction path

    , Article Scientia Iranica ; Volume 21, Issue 3 , 2014 , Pages 945-952 ; ISSN: 10263098 Moezzi, M ; Bakhtiar, M. S ; Sharif University of Technology
    Abstract
    The analysis and design of a tunable low noise active inductor is presented. The noise performance of the proposed gyrator-based active inductor is improved without either degrading its quality factor or consuming more power using a linear Feed Forward Path (FFP). The proposed low noise active inductor has been designed and fabricated using standard 0.18-μm CMOS technology. The measurements show a 3 fold improvement in the input noise current compared to that of conventional active inductors. The active inductor was tuned and measured at the resonance frequency of 2.5 GHz, which could be extended as high as 5.5 GHz, with a quality factor of 30. The circuit draws 4.8 mA from a 1.8 V supply  

    Two-dimensional multi-parameter adaptation of noise, linearity, and power consumption in wireless receivers

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Vol. 61, issue. 8 , July , 2014 , p. 2433-2443 Meghdadi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    Abstract
    This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,... 

    12 bits, 40MS/s, low power pipelined SAR ADC

    , Article Midwest Symposium on Circuits and Systems ; Aug , 2014 , p. 841-844 Khojasteh Lazarjan, V ; Hajsadeghi, K ; Sharif University of Technology
    Abstract
    This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

    A low power 1.2 GS/s 4-bit flash ADC in 0.18 μm CMOS

    , Article Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013 ; 2013 ; 9781479920969 (ISBN) Chahardori, M ; Sharifkhani, M ; Sadughi, S ; Sharif University of Technology
    2013
    Abstract
    A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

    Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation

    , Article Microelectronics Reliability ; Volume 53, Issue 6 , June , 2013 , Pages 912-924 ; 00262714 (ISSN) Rajaei, R ; Tabandeh, M ; Fazeli, M ; Sharif University of Technology
    2013
    Abstract
    In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

    CMOS-compatible structure for voltage-mode multiple-valued logic circuits

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 438-441 ; 9781457718458 (ISBN) Sendi, M. S. E ; Sharifkhani, M ; Sodagar, A. M ; Sharif University of Technology
    Abstract
    This paper presents a low-voltage, CMOS-compatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-μm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V  

    A method for noise reduction in active-rc circuits

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 58, Issue 12 , 2011 , Pages 906-910 ; 15497747 (ISSN) Gharibdoust, K ; Bakhtiar, M. S ; Sharif University of Technology
    Abstract
    A method for noise reduction in active-$RC$ circuits is introduced. It is shown that the output noise in an active-$RC$ circuit can be considerably reduced, without disturbing the circuit transfer function by inserting appropriate passive or active components in the circuit. The inserted components introduce new signal paths in the circuit for noise reduction while the original circuit transfer function is kept unchanged. The procedure to define the proper paths in the circuit and their transfer functions is given. The effectiveness of the presented method is demonstrated using a second-order active-RC filter fabricated in a 0.18-$ {m}$ CMOS technology  

    Low-noise differential transimpedance amplifier structure based on capacitor cross-coupled gm-boosting scheme

    , Article Microelectronics Journal ; Volume 39, Issue 12 , 2008 , Pages 1843-1851 ; 00262692 (ISSN) Jalali, M ; Nabavi, A ; Moravvej Farshi, M. K ; Fotowat Ahmady, A ; Sharif University of Technology
    2008
    Abstract
    This paper presents a capacitor cross-coupled gm-boosting scheme for differential implementation of common-gate transimpedance amplifier (CG-TIA). A differential transimpedance amplifiers (DTIA) is designed by this scheme using two modified floating-biased CG stage with improved low corner frequency. Despite conventional methods for single-ended to differential conversion that increase the power and the noise for the same gain, the new DTIA gives a higher gain and hence reduces the input-referred noise power. Design of the DTIA circuit using 0.13 μm CMOS technology illustrates near 1.7 dB improvement in the circuit sensitivity and 5.2 dB enhancement in transimpedance gain compared to its... 

    A high data-rate energy-efficient interference-tolerant fully integrated CMOS frequency channelized UWB transceiver for impulse radio

    , Article IEEE Journal of Solid-State Circuits ; Volume 43, Issue 4 , 2008 , Pages 974-980 ; 00189200 (ISSN) Medi, A ; Namgoong, W ; Sharif University of Technology
    2008
    Abstract
    A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25-4.75 GHz band designed for low power and high data rate communication is implemented in 0.18 μm CMOS technology. When operating at 1 Gbps data rate, it dissipates 98 mW (98 pJ/b) in the receive-mode and 108 mW (108 pJ/b) in the transmit-mode from a 1.8 V supply [1]. Compared to UWB transceivers reported in the literature, this chip dissipates the lowest energy per bit. In addition, the combination of the frequency channelized architecture, high-linearity RF circuits, aggressive baseband filtering, and low local oscillator spurs results in an interference-tolerant receiver that is able to co-exist with systems operating... 

    Feedback redundancy: A power efficient SEU-tolerant latch design for deep sub-micron technologies

    , Article 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2007, Edinburgh, 25 June 2007 through 28 June 2007 ; 2007 , Pages 276-285 ; 0769528554 (ISBN); 9780769528557 (ISBN) Fazeli, M ; Patooghy, A ; Miremadi, S. G ; Ejlali, A ; Sharif University of Technology
    2007
    Abstract
    The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch where redundant feedback lines are used to mask the effects of SEUs. The power dissipation, area, reliability, and propagation delay of the presented SEU-tolerant latch are analyzed by SPICE simulations. The results show that this latch consumes about 50% less power and occupies 42% less area than a TMR-latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch. the reliability of the proposed latch... 

    A low-area, 0.18μm CMOS, 10Gb/s optical receiver analog front end

    , Article 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, New Orleans, LA, 27 May 2007 through 30 May 2007 ; 2007 , Pages 3904-3907 ; 02714310 (ISSN) Maadani, M ; Atarodi, M ; Sharif University of Technology
    2007
    Abstract
    A fully integrated, low-cost (area), low-power, high-gain, differential Optical Receiver Analog Front-End (AFE), including Transimpedance Amplifier (TIA), Limiting Amplifier (LA), DC-Offset Cancellation Feedback and Output-Buffer is designed in TSMC 0.18μm CMOS Technology. The optimized TIA has a Regulated Cascode (RGC) topology, with 5.9mW power-dissipation, 48 dBΩ gain, 8.46GHz bandwidth. The Proposed Limiting Amplifier (LA) has an Inductor-Less topology, with 41.9dB gain, 91.1mW power consumption (including Output Buffer), output swing of 0.4VP-P, and bandwidth of 7.88GHz (Output-Buffer applied), using Built-in Active Inductors and Negative Miller Capacitance to broaden the bandwidth. The...