Sharif Digital Repository

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch... 

An analytic method for prediction of oscillation amplitude and supply current of differential CMOS oscillators is presented. The validity of this method has been verified by designing an LC CMOS oscillator in a 0.24 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of supply voltage  

A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from... 

This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW  

In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply. © 2007 IEEE  

An 8-bit High-speed folding/interpolating ADC is presented. Designed in 0.18μm CMOS technology, the ADC dissipates only 50mW from a single 1.5V supply. A novel technique based on using both N and P folding cells is used to widen the input range and a self-calibration technique based on using Trimmable MOSFETs is employed to improve the static and dynamic performance  

A novel, precision current reference with low temperature and supply sensitivity and without any external component has been designed in a 0.18μm CMOS mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit like a beta multiplier. The simulation results show max-to-min fluctuation of about 1% over a temperature range of -20°C to +100°C and supply voltage range of 1.1V to 2V with ±30% tolerance for all of the used on-chip resistors. The maximum nominal current variation in process corners is less than 3.5%. © 2003 IEEE  

Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques  

In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008  

During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable... 

A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE  

In this paper, we propose a new voltage controlled oscillator (VCO) with a high oscillation frequency yet low power consumption. The oscillator which is a single stage circuit has a low phase noise due to reduced noise sources. To evaluate the performance parameters, the oscillator was simulated in a 0.18-μm standard CMOS process. The results show that the oscillation frequency of VCO may vary between 4.66-5.9 GHz. Also, the phase noise of the VCO at oscillation frequency of 5.6 GHz is -99.7 dBc at 1 MHz offset frequency. Also, the power consumption was 4.8 mW at the same oscillation frequency. © 2007 IEEE  

A high speed, high resolution switched-current sample and hold (SI S/H) based on a new class AB transconductance stage is presented. Simulations performed on the SI S/H in standard 0.18um CMOS technology with 1.5v supply voltage indicate low power dissipation, high sampling speed and high SNR. © 2006 IEEE  

In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18μm CMOS process show a THD of less than 44dB for 0.6Vpp input signal and an input-referred noise of less than 45 nV/√Hz in worst case. The current consumption of each OTA is 1.5-mA. © 2006 IEEE  

The analysis and design of a tunable low noise active inductor is presented. The noise performance of the proposed gyrator-based active inductor is improved without either degrading its quality factor or consuming more power using a linear Feed Forward Path (FFP). The proposed low noise active inductor has been designed and fabricated using standard 0.18-μm CMOS technology. The measurements show a 3 fold improvement in the input noise current compared to that of conventional active inductors. The active inductor was tuned and measured at the resonance frequency of 2.5 GHz, which could be extended as high as 5.5 GHz, with a quality factor of 30. The circuit draws 4.8 mA from a 1.8 V supply  

This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,... 

This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

This paper presents a low-voltage, CMOS-compatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-μm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V