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Total 125 records

    A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 1- 5 June , 2014 , pp. 1147-1150 ; ISSN: 02714310 Esmaeelzadeh, H ; Sharifkhani, M ; Shabany, M ; Sharif University of Technology
    Abstract
    This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW  

    An 8-bit current-mode folding ADC with optimized active averaging network

    , Article Scientia Iranica ; Volume 15, Issue 2 , 2008 , Pages 151-159 ; 10263098 (ISSN) Azin, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    Sharif University of Technology  2008
    Abstract
    In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008  

    On the importance of the number of fanouts to prevent the glitches in DPA-resistant devices

    , Article 13th International Computer Society of Iran Computer Conference on Advances in Computer Science and Engineering, CSICC 2008, Kish Island, 9 March 2008 through 11 March 2008 ; Volume 6 CCIS , 2008 , Pages 661-670 ; 18650929 (ISSN); 3540899847 (ISBN); 9783540899846 (ISBN) Moradi, A ; Salmasizadeh, M ; Manzuri Shalmani, M. T ; Sharif University of Technology
    2008
    Abstract
    During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable... 

    A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer

    , Article APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30 November 2008 through 3 December 2008 ; 2008 , Pages 1383-1386 ; 9781424423422 (ISBN) Saeedi, S ; Atarodi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    2008
    Abstract
    A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE  

    A tunable high-Q active inductor with a feed forward noise reduction path

    , Article Scientia Iranica ; Volume 21, Issue 3 , 2014 , Pages 945-952 ; ISSN: 10263098 Moezzi, M ; Bakhtiar, M. S ; Sharif University of Technology
    Abstract
    The analysis and design of a tunable low noise active inductor is presented. The noise performance of the proposed gyrator-based active inductor is improved without either degrading its quality factor or consuming more power using a linear Feed Forward Path (FFP). The proposed low noise active inductor has been designed and fabricated using standard 0.18-μm CMOS technology. The measurements show a 3 fold improvement in the input noise current compared to that of conventional active inductors. The active inductor was tuned and measured at the resonance frequency of 2.5 GHz, which could be extended as high as 5.5 GHz, with a quality factor of 30. The circuit draws 4.8 mA from a 1.8 V supply  

    Two-dimensional multi-parameter adaptation of noise, linearity, and power consumption in wireless receivers

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Vol. 61, issue. 8 , July , 2014 , p. 2433-2443 Meghdadi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    Abstract
    This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,... 

    12 bits, 40MS/s, low power pipelined SAR ADC

    , Article Midwest Symposium on Circuits and Systems ; Aug , 2014 , p. 841-844 Khojasteh Lazarjan, V ; Hajsadeghi, K ; Sharif University of Technology
    Abstract
    This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

    A low power 1.2 GS/s 4-bit flash ADC in 0.18 μm CMOS

    , Article Proceedings of IEEE East-West Design and Test Symposium, EWDTS 2013 ; 2013 ; 9781479920969 (ISBN) Chahardori, M ; Sharifkhani, M ; Sadughi, S ; Sharif University of Technology
    2013
    Abstract
    A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

    Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation

    , Article Microelectronics Reliability ; Volume 53, Issue 6 , June , 2013 , Pages 912-924 ; 00262714 (ISSN) Rajaei, R ; Tabandeh, M ; Fazeli, M ; Sharif University of Technology
    2013
    Abstract
    In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

    CMOS-compatible structure for voltage-mode multiple-valued logic circuits

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 438-441 ; 9781457718458 (ISBN) Sendi, M. S. E ; Sharifkhani, M ; Sodagar, A. M ; Sharif University of Technology
    Abstract
    This paper presents a low-voltage, CMOS-compatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-μm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V  

    A method for noise reduction in active-rc circuits

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 58, Issue 12 , 2011 , Pages 906-910 ; 15497747 (ISSN) Gharibdoust, K ; Bakhtiar, M. S ; Sharif University of Technology
    Abstract
    A method for noise reduction in active-$RC$ circuits is introduced. It is shown that the output noise in an active-$RC$ circuit can be considerably reduced, without disturbing the circuit transfer function by inserting appropriate passive or active components in the circuit. The inserted components introduce new signal paths in the circuit for noise reduction while the original circuit transfer function is kept unchanged. The procedure to define the proper paths in the circuit and their transfer functions is given. The effectiveness of the presented method is demonstrated using a second-order active-RC filter fabricated in a 0.18-$ {m}$ CMOS technology  

    Low-noise differential transimpedance amplifier structure based on capacitor cross-coupled gm-boosting scheme

    , Article Microelectronics Journal ; Volume 39, Issue 12 , 2008 , Pages 1843-1851 ; 00262692 (ISSN) Jalali, M ; Nabavi, A ; Moravvej Farshi, M. K ; Fotowat Ahmady, A ; Sharif University of Technology
    2008
    Abstract
    This paper presents a capacitor cross-coupled gm-boosting scheme for differential implementation of common-gate transimpedance amplifier (CG-TIA). A differential transimpedance amplifiers (DTIA) is designed by this scheme using two modified floating-biased CG stage with improved low corner frequency. Despite conventional methods for single-ended to differential conversion that increase the power and the noise for the same gain, the new DTIA gives a higher gain and hence reduces the input-referred noise power. Design of the DTIA circuit using 0.13 μm CMOS technology illustrates near 1.7 dB improvement in the circuit sensitivity and 5.2 dB enhancement in transimpedance gain compared to its... 

    A high data-rate energy-efficient interference-tolerant fully integrated CMOS frequency channelized UWB transceiver for impulse radio

    , Article IEEE Journal of Solid-State Circuits ; Volume 43, Issue 4 , 2008 , Pages 974-980 ; 00189200 (ISSN) Medi, A ; Namgoong, W ; Sharif University of Technology
    2008
    Abstract
    A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25-4.75 GHz band designed for low power and high data rate communication is implemented in 0.18 μm CMOS technology. When operating at 1 Gbps data rate, it dissipates 98 mW (98 pJ/b) in the receive-mode and 108 mW (108 pJ/b) in the transmit-mode from a 1.8 V supply [1]. Compared to UWB transceivers reported in the literature, this chip dissipates the lowest energy per bit. In addition, the combination of the frequency channelized architecture, high-linearity RF circuits, aggressive baseband filtering, and low local oscillator spurs results in an interference-tolerant receiver that is able to co-exist with systems operating... 

    Spectrum Sensing Algorithm and Implementation for Cognitive Radio Applications

    , M.Sc. Thesis Sharif University of Technology Katanbaf Nezhad, MohamadTaghi (Author) ; Fotowat Ahmadi, Ali (Supervisor)
    Abstract
    The continous growth of wireless networks, the increasing numbers of users and devices, along with the demand for higher data rates have intensified the frequency band limitations as the communication medium. In search for more efficient methods to use this limited resource, the cognitive radio approach that allocates the local unused frequency bands to potential users has attracted considerable attension.
    A fundamental and unseperable part of any cognitive radio system is its need to search, detect and understand the surrounding frequency spectrum. Although various methods have been already propose to overcome the challenges of this domain, simpler and more reliable methods are still in... 

    Design method for a reconfigurable CMOS LNA with input tuning and active balun

    , Article AEU - International Journal of Electronics and Communications ; Vol. 69, issue. 1 , January , 2014 , p. 424-431 Akbar, F ; Atarodi, M ; Saeedi, S ; Sharif University of Technology
    Abstract
    A method to design a tunable low noise amplifier (LNA) for multiband receivers is proposed. This paper also presents a single-ended to differential conversion (S2DC) topology which improves the LNA linearity without degrading its noise performance. Combining input tuning with S2DC in a single stage reduces power consumption of the LNA and decreases effects of supply noise. An LNA has been designed based on the proposed method for 2.3-4.8 GHz in a 0.18 μm CMOS technology. Simulations show an IIP3 of -3.2 dBm, a less than 3.7 dB noise figure (NF), a voltage gain of 24 dB in the whole frequency range. The LNA draws 13.1 mW from a 1.8 V supply. The results indicate that the proposed tuning... 

    An auto-calibrated, dual-mode SRAM macro using a hybrid offset-cancelled sense amplifier

    , Article Microelectronics Journal ; Vol. 45, issue. 6 , 2014 , p. 781-792 Attarzadeh, H ; Sharifkhani, M ; Sharif University of Technology
    Abstract
    A dual-mode power and performance optimized SRAM is presented. Given the fact that the power and speed associated with the cell access time are directly related to the sense amplifier offset a new optimization platform based on the hybrid offset-cancelled current sense amplifier (OCCSA) [1] is presented. It is shown that the speed and power overhead of the offset cancellation can be optimized in a multi-variable auto-calibration loop to achieve the lowest power or the highest performance mode. The flexibility of having two degrees of freedom in OCCSA offers a significant bitline delay reduction with minimum power sacrifice in the high performance mode. The proposed scheme is verified using a... 

    A 90 nm-CMOS IR-UWB BPSK transmitter with spectrum tunability to improve peaceful UWB-narrowband coexistence

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Vol. 61, issue. 6 , January , 2014 , p. 1836-1848 ; 15498328 Mir-Moghtadaei, S. V ; Fotowat-Ahmady, A ; Nezhad, A. Z ; Serdijn, W. A ; Sharif University of Technology
    Abstract
    A new ultra wideband (UWB) pulse generator covering a-10 dB bandwidth of 2.4-4.6 GHz with a tunable center frequency of 5-5.6 GHz to mitigate coexistence issues of impulse radio UWB (IR-UWB) systems and IEEE802.11.a WLAN or other narrowband (NB) systems in 90 nm-CMOS technology is proposed. The UWB pulse is generated based on frequency up-conversion of the first derivative of the Gaussian pulse, which creates an adjustable null in the frequency spectrum. Simulation results show that employing the proposed pulse generator mitigates the mutual interference between UWB and WLAN systems, significantly. The proposed transmitter consists of a low frequency signal generator, an LC oscillator and a... 

    An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2013 , Pages 797-800 ; 02714310 (ISSN) ; 9781467357609 (ISBN) Ardakani, A ; Mahdavi, M ; Shabany, M ; Sharif University of Technology
    2013
    Abstract
    Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design... 

    A UHF-RFID transceiver with a blocker-canceller feedback and 30 dBm output power

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 60, Issue 11 , 2013 , Pages 3043-3054 ; 15498328 (ISSN) Ghahremani, A ; Rezaei, V. D ; Bakhtiar, M. S ; Sharif University of Technology
    2013
    Abstract
    A single chip UHF-RFID transceiver front-end is presented. The chip was designed according to EPCglobal Class-1 Gen-2 and supports both ETSI and FCC requirements. The receiver front end is capable of rejecting self-jammers as large as 10 dBm with the aid of a feedback loop. The stability and the robustness of the loop and other system requirements are studied. A 30 dBm class-AB power amplifier (PA) with 28% PAE is also integrated on the chip. The pseudo differential architecture of the PA greatly reduces the injection of the signal into the substrate. A simple model is used to estimate the effect of the substrate noise injection by the PA on the receiving circuit modules and design guides... 

    A layout-based approach for multiple event transient analysis

    , Article Proceedings - Design Automation Conference ; 2013 ; 0738100X (ISSN) ; 9781450320719 (ISBN) Ebrahimi, M ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    2013
    Abstract
    With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). In this paper, a fast and accurate layout- based Soft Error Rate (SER) estimation technique with consideration of both SET and MET fault models is pro- posed. Unlike previous techniques in which the adjacent MET sites are obtained from logic-level netlist, we perform a comprehensive layout analysis to extract MET adjacent cells. It is shown that layout-based technique is the only effective solution for identification of adjacent cells as netlist-based techniques significantly underestimate the overall SER....