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CMOS-compatible structure for voltage-mode multiple-valued logic circuits

Sendi, M. S. E ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1109/ICECS.2011.6122307
  3. Abstract:
  4. This paper presents a low-voltage, CMOS-compatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-μm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V
  5. Keywords:
  6. Multiple-valued logic circuit ; MAX circuit ; Multiple valued logic ; Quaternary inverter ; Quaternary latch ; Voltage mode ; CMOS integrated circuits ; Flip flop circuits ; Many valued logics ; Logic circuits
  7. Source: 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 438-441 ; 9781457718458 (ISBN)
  8. URL: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6122307