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An X-Band Class-J Power Amplifier with Active Load Modulation to Boost Drain Efficiency

Alizadeh, A ; Sharif University of Technology | 2020

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  1. Type of Document: Article
  2. DOI: 10.1109/TCSI.2020.2991184
  3. Publisher: Institute of Electrical and Electronics Engineers Inc , 2020
  4. Abstract:
  5. In this paper, the performance of the class-J mode power amplifier (PA) is studied when an auxiliary network performs active load modulation on the main transistor. Load modulation is realized by injecting an additional class-C like current with conduction angle of $alpha $ to the drain node of the main transistor. The injected current employs a phase shift of $phi $ with respect to the half-sinusoidal current of the main transistor, and its maximum value is tuned with the size of the transistor used in the auxiliary network. Detailed theoretical formulations are presented for the optimal load impedances of the PA at the fundamental and second-harmonic frequencies. Furthermore, the output power and drain efficiency of the PA are derived, and it is shown that the drain efficiency of the proposed PA can be as high as 96.8% in theory. The optimal values of $alpha $ and $phi $ for improving the drain efficiency of the load-modulated class-J PA are obtained, and a design methodology is also proposed to choose the optimal size of the transistor employed in the auxiliary network. To verify the theoretical derivations, a proof-of-concept 0.83 W class-J PA was designed and fabricated in a 0.25 $mu ext{m}$ GaAs pHEMT process. The designed PA occupies 3.19 mm2 die area, and it achieves 71% drain-efficiency and 50% power-added-efficiency at 10 GHz. © 2004-2012 IEEE
  6. Keywords:
  7. Class-J ; Class-J₂ ; Continuous-mode power amplifiers ; High-efficiency power amplifiers ; Efficiency ; Gallium arsenide ; III-V semiconductors ; Modulation ; Power amplifiers ; Transistors ; Auxiliary network ; Design Methodology ; Gaas phemt process ; Power-added efficiency ; Proof of concept ; Sinusoidal currents ; Theoretical derivations ; Theoretical formulation ; Drain current
  8. Source: IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 67, Issue 10 , 2020 , Pages 3364-3377
  9. URL: https://ieeexplore.ieee.org/document/9090329