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Handling hard errors in PCMs by using intra-line level schemes

Asadinia, M ; Sharif University of Technology | 2020

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  1. Type of Document: Article
  2. DOI: 10.1016/bs.adcom.2019.10.003
  3. Publisher: Academic Press Inc , 2020
  4. Abstract:
  5. In this chapter, we first introduce one shifting mechanisms in order to further prolonging the lifetime of a phase change memory (PCM) device, reducing the write rate to PCM cells, and handling cell failures when hard faults occur. In this line, Byte-level Shifting Scheme (BLESS) is addressed and reduces write pressure over hot cells of blocks. Additionally, we illustrate that using the MLC capability of PCM and manipulating the data block to recover faulty cells can also be used for error recovery purpose. Next, we propose another intra-line level pairing scheme (ILP). This novel recovery mechanism can statically partition a data block into a small number of groups and efficiently benefits from the advantages of MLC capability and enables word-pairing mechanism within a line. © 2020 Elsevier Inc
  6. Keywords:
  7. Data block partitioning ; Endurance ; Hard error ; Memory bit flip uniformity ; Memory block shifting ; Multi-level cell PCM ; Phase change memory
  8. Source: Advances in Computers ; Volume 118 , 2020 , Pages 79-109
  9. URL: https://www.sciencedirect.com/science/article/pii/S0065245819300567