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Phase-change memory architectures

Asadinia, M ; Sharif University of Technology | 2020

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  1. Type of Document: Article
  2. DOI: 10.1016/bs.adcom.2019.10.001
  3. Publisher: Academic Press Inc , 2020
  4. Abstract:
  5. Some of the recent approaches regarding leverage PCM will be reviewed in this chapter. The chapter starts with a discussion regarding future main memory systems that includes hybrid architecture schemes using both PCM and DRAM arrays. Later, we focus on PCM only approaches and this section will help describe some techniques for reducing the increased read latency because of slow writes in PCMs. In this chapter, we also illustrate wear-leveling approaches and review the security problems of this memory approach which are lifetime limited. This section includes an overview of the recent security aware wear-leveling techniques, whose methods help detect attacks, and their issues during the runtime. Finally, we describe efficient schemes with hard error detection and correction capabilities as well as soft error problems like resistance drift. © 2020 Elsevier Inc
  6. Keywords:
  7. Byte-level compression ; Endurance ; Fault model ; Hard error correction ; Hard error detection ; Hybrid memory ; Phase change memory ; Soft error issues
  8. Source: Advances in Computers ; Volume 118 , 2020 , Pages 29-48
  9. URL: https://www.sciencedirect.com/science/article/pii/S0065245819300543