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A high-performance architecture for irregular LDPC decoding algorithm using input-multiplexing method

Sarbishei, O ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/ISSPA.2007.4555291
  3. Publisher: 2007
  4. Abstract:
  5. A new high-performance architecture for decoding the irregular Low-Density Parity-Check (LDPC) codes with respect to the iterative message-passing decoding algorithm is explored. The proposed method is based on reducing the logic delays in the iterative processing of the bit nodes and check nodes leading to the increment of maximum possible frequency. The simulations show the efficiency of the proposed method in low/high-complexity graph matrices, though it is more effective in high-complexity ones. About 28% reduction of the combinational delay in the bit/check processors is explored without much impacting the area consumption. ©2007 IEEE
  6. Keywords:
  7. Boolean functions ; Decoding ; Image coding ; Ketones ; Message passing ; Multiplexing ; Signal processing ; High-performance architectures ; International symposium ; Iterative decoding
  8. Source: 2007 9th International Symposium on Signal Processing and its Applications, ISSPA 2007, Sharjah, 12 February 2007 through 15 February 2007 ; 2007 ; 1424407796 (ISBN); 9781424407798 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4555291