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An on-line BIST technique for delay fault detection in CMOS circuits

Moghaddam, E ; Sharif University of Technology | 2007

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  1. Type of Document: Article
  2. DOI: 10.1109/ATS.2007.4387986
  3. Publisher: 2007
  4. Abstract:
  5. This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented. © 2007 IEEE
  6. Keywords:
  7. Built-in self test ; Delay circuits ; Electric fault currents ; Fault detection ; Switching circuits ; Switching theory ; Testing ; BIST techniques ; CMOS circuits ; CMOS logic circuits ; Delay fault ; Delay faults ; Delay-fault testing ; Design for testability ; Logic families ; Online testing ; Pattern generation ; Robust delay test ; Simulation results ; Simulation-based ; Logic circuits
  8. Source: 16th Asian Test Symposium, ATS 2007, Beijing, 8 October 2007 through 11 October 2007 ; November , 2007 , Pages 73-76 ; 10817735 (ISSN); 0769528902 (ISBN); 9780769528908 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/4387986