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A wide tuning range, fractional multiplying delay-locked loop topology for frequency hopping applications

Tajalli, A ; Sharif University of Technology | 2006

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  1. Type of Document: Article
  2. DOI: 10.1007/s10470-006-1276-7
  3. Publisher: 2006
  4. Abstract:
  5. This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between two consecutive integer numbers. Operating in 2.5 GHz, total circuit including digital part consumes 15.5 mW from 1.8 V supply voltage. At the proposed architecture, reference clock is injected into a ring oscillator in specified times and to the specified delay-stages to synthesize the fractional frequency multiplication as well as resetting the accumulated jitter during previous cycles. Operating in maximum speed, simulated RMS (root-mean-square) and PTP (peak-to-peak) jitter values are 1.8 and 14.5 ps, respectively, while the settling time is 5 us. © 2006 Springer Science + Business Media, Inc
  6. Keywords:
  7. Clock generators ; Delay-locked loops ; Fractional DLL ; Frequency synthesizer ; Frequency hopping ; Frequency multiplying circuits ; Jitter ; Oscillators (electronic) ; Topology ; Tuning ; Networks (circuits)
  8. Source: Analog Integrated Circuits and Signal Processing ; Volume 46, Issue 3 , 2006 , Pages 203-214 ; 09251030 (ISSN)
  9. URL: https://link.springer.com/article/10.1007/s10470-006-1276-7