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Hierarchical Graph: A new cost effective architecture for network on chip

Vahdatpour, A ; Sharif University of Technology | 2005

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  1. Type of Document: Article
  2. DOI: 10.1007/11596356_33
  3. Publisher: 2005
  4. Abstract:
  5. We purposed a new Network on Chip (NoC) architecture called Hierarchical Graph. The most interesting feature of this novel architecture is its simple implementation process. Furthermore, the flexible structure of this topology makes it suitable for use in application specified chips. To benchmark the suggested architecture with existing ones, basic models of physical implementation have been extracted and simulated using NS-2. The results compared with the common used architecture Mesh show that HG has better performance, especially in local traffics and high loads. © IFIP International Federation for Information Processing 2005
  6. Keywords:
  7. Application specified chips ; Hierarchical Graph ; Implementation process ; Network on chip (NoC) ; Benchmarking ; Computer networks ; Hierarchical systems ; Telecommunication traffic ; Topology ; Microprocessor chips
  8. Source: International Conference on Embedded and Ubiquitous Computing, EUC 2005, Nagasaki, 6 December 2005 through 9 December 2005 ; Volume 3824 LNCS , 2005 , Pages 311-320 ; 03029743 (ISSN); 3540308075 (ISBN); 9783540308072 (ISBN)
  9. URL: https://link.springer.com/chapter/10.1007/11596356_33