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A 1-V 400MS/s 14bit self-calibrated CMOS DAC with enhanced dynamic linearity

Saeedi, S ; Sharif University of Technology | 2004

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  1. Type of Document: Article
  2. Publisher: 2004
  3. Abstract:
  4. A 1-V CMOS current steering digital to analog converter with enhanced static and dynamic linearity is presented. The 14-bit static linearity is achieved by a novel background analog self calibration technique which is suitable for low voltage applications and does not require error measurement and correction circuits. To improve dynamic linearity at high frequencies, a new low power track/attenuate output stage is used at the DAC output. Integral and differential nonlinearities of the proposed DAC corresponding, to 14-bit specification are less than 0.35LSB and 0.25LSB, respectively. The DAC is functional up to 400MS/S with SFDR better than 71dB in the Nyquist band. The circuit has been designed and simulated in a standard 0.18u CMOS technology
  5. Keywords:
  6. Digital to analog converter (DAC) ; Dynamic nonlinearities ; Self calibration ; Track/attenuate output stage
  7. Source: 2004 IEEE International Symposium on Circuits and Systems - Proceedings, Vancouver, BC, 23 May 2004 through 26 May 2004 ; Volume 1 , 2004 , Pages I349-I352 ; 02714310 (ISSN)
  8. URL: https://ieeexplore.ieee.org/document/1328203