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- Type of Document: M.Sc. Thesis
- Language: Farsi
- Document No: 55931 (05)
- University: Sharif University of Technology
- Department: Electrical Engineering
- Advisor(s): Sharif Khani, Mohammad
- Abstract:
- Analog to digital converters is one of the main building blocks of today's circuits. These circuits play an important role in signal processing. Since these circuits consist of analog and digital sections, a large percentage of the power consumed in a circuit is allocated to this section. Therefore, in applications such as medical devices, wearable applications and wireless technology where power control is very important and necessary, reducing the power of analog to digital converters is very important. One of the simplest analog-to-digital converters from the design point of view is Successive Approximation Register (SAR) analog-to-digital converters. This type of analog-to-digital converters is widely used in applications that require an accuracy of 8-10 bits and a sampling rate range of a few KHz to several tens of MHz. This type of converters has low power consumption due to their simplicity in structure and their design is not very challenging up to 10-bit accuracy. At accuracies higher than 10 bits, it becomes very difficult to design because of the limited accuracy of analog blocks. Also, in high accuracy, a digital-to-analog converter with higher accuracy is needed, which will increase the overall power of the SAR converter and reduce the efficiency of the converter. Based on this, in this thesis, while reducing the power of the analog to digital converter, a successive approximation method is proposed to improve its accuracy. In the analog to digital SAR converter, the power consumption of the digital to analog converter increases exponentially with the increase in the accuracy of the converter, and since this power is proportional to the square of the supply voltage, therefore, in order to reduce the power consumption, in the proposed structures, the supply voltage is half of the nominal value of the technology. Use is selected. Also, to reduce the consumption area caused by the capacitive digital to analog converter with a weighted capacitor, the structure of the C-2C capacitive digital to analog converter has been used, and the use of this structure can help to reduce the power consumption and also to reduce the consumption area. Also, since a part of the power is lost in the circuit at the moments when the circuit does not function, an asynchronous structure has been used, which does not require an external crystal or oscillator, only by applying a pulse with a suitable width, the circuit can be turned on. Using this method makes the circuit not always on and reduces the power consumption. The sampling rate of this converter can be adjusted from 100 KS/Sec to 500 KS/Sec. By simulating this circuit, we reached a power consumption of about 400 nW and an accuracy of 8.7 bits. Reducing the voltage of the power supply leads to a decrease in the swing of the circuit and this will cause a decrease in the signal-to-noise ratio in the circuit, hence the Noise Shaping SAR structure is used to improve the SNR value of the circuit by using oversampling technique. Gives. To confirm the efficiency of this method, an NS-SAR converter with a 0.5V power supply in 65nm technology, with a sampling rate of 500k samples/second, has been designed and simulated. By using this method, the accuracy of the converter has increased from 8.7 bits to 11 bits, and its total power consumption is around 1.1 microwatts, which finally reached the FOM of 8.59 (fj/conv.step) and 172.51 [dB]
- Keywords:
- Analog to Digital Converter ; Successive Approximation Register (SAR) ; Noise Shaping ; Capacitive Digital To Analog Converter ; Oversampling ; C-2C Capacitive Digital-to-Analog Converter
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