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Investigation of Modeling and Implementation of Systolic Arrays on Accelerators

Zarei, Parisa | 2023

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 55820 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Ghodsi, Mohammad
  7. Abstract:
  8. The ever-increasing volume of data and calculations has caused a noticeable increase in the importance of computer processing speed. Therefore, topics related to parallel processing as an effective solution in increasing the speed of calculations have been specially investigated and studied. Systolic computing is a powerful approach to parallelize data and perform concurrent computations. Systolic arrays fulfill the goals of the algorithm by directing data flow among different processors and performing minor calculations on them. The slowness and limitations of processors compatible with these arrays, such as FPGAs, have faced many challenges in applying and using their capacities. These challenges have caused systolic arrays to be largely excluded from research and development. On the other hand, the growing procedure and improvements of computers based on multi-core processors have provided a suitable platform for performing fast calculations. Therefore, the integration of the concepts of systolic arrays and multi-core hardware such as GPUs can help increase performance and efficiency, but the mismatch be- tween the architecture of systolic arrays and the architecture of GPUs, their implementation on GPU make some challenges.In this research, while reviewing the research related to the imple- mentation of systolic networks on FPGA and GPU, by analyzing the existing methods, we have presented a method for modeling and mapping systolic arrays on GPUs that support CUDA. Then, by implementing different algorithms, we have evaluated the efficiency of the presented method. This method is presented as an elementary but effective method for mapping systolic arrays on GPUs, the results of which are promising for high-performance parallel computing in the future. Also, at the end of this research, we have mentioned the huge research capacities of this field
  9. Keywords:
  10. Parallel Processing ; Systolic Array ; Computers Based on Multi-Core Processors ; Fast Computation ; Computed Unified Device Architecture (CUDA)Platform ; Accelerators

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