Design of a Low Power Monotonic SAR ADC with Offset Flattening

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Fateminia, Mohammad Javad | 2018

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 51785 (05)
University: Sharif University of Technology
Department: Electrical Engineering
Advisor(s): Sharifkhani, Mohammad
Abstract:
The successive approximation digital to analog converters are appropriate selection for use in new technologies and low-powered applications. Despite the low power consumption of this kind of converters, there are some applications like medical which require very low power consumption. In order to reduce the power consumption of SAR ADC, capacitive digital to analog converters and comparators are great importance. In this Thesis, monotonic switching method has been used, the switching power of this method is lower than the conventional method by 81.2%. Since the common mode of the output of this type of switch is variable, the offset is sensitive and requires a technique to resolve this sensitivity. In this Thesis, a method called flattening offset has been proposed that would neutralize the effect of modal changes on offset. Using the proposed method, a converter with 50 MS/s sampling rate and the precision of 12 bits in the TSMC 65 nm technology was designed to simulate with a power consumption of 1.4 mW and the signal to noise ratio of 63.1 dB and 33.2 fJ/Conv.Step figure of merit achieved. The designed converter is used in ultrasound imaging
Keywords:
Analog to Digital Converter ; Monotonic Switching ; Offset Flattening ; Successive Approximation Register (SAR) ; Power Consumption

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