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Instruction Cache Miss Rate Reduction with Timely Next-Line Prefetching

Ansari, Ali | 2019

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 52418 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. The frontend stalls caused by instruction cache and branch target buffer (BTB) misses are a well-known source of performance degradation in server processors.To address this limitation, a myriad of hardware prefetchers are proposed. While they can effectively eliminate lots of misses and increase performance, they are impractical solutions due to some shortcomings. In this study, we are looking for effective and practical solutions to address these limitations.Since the considerable fraction of instruction cache misses is sequential misses,sequential prefetchers like next-line prefetcher are simple and effective solutions to remove sequential misses that are used in modern server processors. However,their efficiency is limited because of poor timeliness and considerable useless prefetches which resolving each issue results in degrading the other one. In other words, increasing the prefetcher’s depth was the solution to address the timeliness problem but using this approach significantly increases the useless prefetches.Based on this observation, we have proposed a mechanism that provides both timely and accurate prefetches for sequential prefetchers. The proposed mechanism needs 2 KB storage overhead and eliminates almost all sequential misses in server workloads.By exploiting a powerful sequential prefetcher, we also augment it with simple discontinuity and BTB prefetchers to address all parts of the frontend bottleneck.While discontinuity and BTB prefetchers are well-known solutions, our proposed prefetchers have some advantages including lower storage overhead and more practical design. The proposed mechanism needs just 7.3 KB storage budget and outperforms state-of-the-art prefetchers by 5% on average and up to 16%
  9. Keywords:
  10. Server Workloading ; Instruction Prefetching ; Cache Miss Prediction ; Branch Target Buffer Miss ; Sequential Prefetcher ; Branch Target Buffer (BTB)

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