Loading...
Switch level fault emulation
50 viewed

Switch level fault emulation

Miremadi, S. G

Switch level fault emulation

Miremadi, S. G ; Sharif University of Technology | 2003

50 Viewed
  1. Type of Document: Article
  2. DOI: 10.1007/978-3-540-45234-8_82
  3. Publisher: Springer Verlag , 2003
  4. Abstract:
  5. The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch level models. © Springer-Verlag Berlin Heidelberg 2003
  6. Keywords:
  7. CMOS integrated circuits ; Fault detection
  8. Source: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) ; Volume 2778 , 2003 , Pages 849-858 ; 03029743 (ISSN); 3540408223 (ISBN); 9783540408222 (ISBN)
  9. URL: https://link.springer.com/chapter/10.1007/978-3-540-45234-8_82