Sharif Digital Repository

A comparator comprises a cross coupled circuit which produces a positive feedback. In conventional comparators, the mismatch between the cross coupled circuits determines the trade-off between the speed, offset and the power consumption of the comparator. A new low-offset low-power dynamic comparator for analog-to-digital converters is introduced. The comparator benefits from two stages and two operational phases to reduce the offset voltage caused by the mismatch effect inside the positive feedback circuit. Rigorous statistical analysis yields the input referred offset voltage and the delay of the comparator based on the circuit random parameters. The derivations are verified with... 

Computationally exhaustive time-domain Monte Carlo (MC) simulations are commonly conducted to obtain the static characteristics of a residual analog-to-digital converter (ADC) (e.g., pipelined ADC) for the calculation of the integral nonlinearity (INL) and differential nonlinearity (DNL). In this brief, a new ultrahigh-speed, yet precise, behavioral-level dc characterization algorithm for residual-based ADC is introduced. The algorithm derives the transition points of a given stage of the ADC based on the random parameters of that stage. Then, it merges the dc characteristics of all stages together to extract detailed dc input-output characteristics for the entire ADC. Then, the exact amount... 

In this article, we present a new iterative algorithm aimed at improving the performance of the sigma-delta analog to digital (A/D) converter. We subject the existing sigma-delta modulator, without changing the configuration, to an iterative procedure to increase the signal-to-noise ratio of the reconstructed signal. In other words, we demonstrate that sigma-delta modulated signals can be decoded using the iterative algorithm. Simulation results confirm that the proposed method works very well, even when less complex filters are used. The simple and regular structure of this new A/D converter, not only makes realization of the hardware as ASIC or on FPGA boards easy, but also allows it to... 

A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous... 

A new modeling and analysis of the nonlinearities caused by the capacitor mismatch errors in the pipeline analog-to-digital converters (ADCs) is presented. Error in each stage is modeled by an input-referred gain error and a nonlinear term. A method is proposed for calculation of the ADC integral nonlinearity (INL) from the total input referred error. Analytical expressions for estimation of the ADC INL in terms of standard deviation of random capacitor mismatch errors are derived. The proposed model is verified by system-level Monte Carlo simulations  

Level-crossing (LC) analog-to-digital (A/D) converters can efficiently sample certain classes of signals. An LC A/D converter is a real-time asynchronous system, which encodes the information of an analog signal into a sequence of nonuniformly spaced time instants. In particular, this class of A/D converters uses an asynchronous data conversion approach, which is a power efficient technique. In this study, the authors propose adaptive and multi-level adaptive LC sampling models as alternatives to conventional LC schemes and apply an iterative algorithm to improve the reconstruction quality of LC A/D converters. This simulation results show that multi-level adaptive LC outperforms... 

In this paper, we present and analyze a novel all-optical multilevel multiclass optical code division multiple access (OCDMA) system, using optical analog-to-digital converter (ADC) and advanced optical logic gate elements. In such OCDMA network, users are distributed in Mdifferent classes. Furthermore, power level with which users in class j,j = 2⋯M, transmit optical pulses, is twice the power level at which users of class j - 1transmit their optical pulses. We achieve optical transmitter structure that satisfies these conditions using power control schemes. Also, we suggest two receiver structures for the aforementioned multiclass multilevel system. The first and simple receiver structure... 

This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18μm CMOS technology and achieves 84dB dynamic range for a 10MHz signal bandwidth. Total analog power dissipation measured was 44mW  

Time-interleaved analog to digital converters (TI-ADC) offer high sampling rates by passing the input signal through C parallel low-rate ADCs. We can achieve C-times the sampling rate of a single ADC if all the shifts between the channels are identical. In practice, however, it is not possible to avoid mismatch among shifts. Besides, the samples are also subject to jitter noise. In this paper, we propose a blind method to mitigate the joint effects of sampling jitter and shift mismatch in the TI-ADC structure. We assume the input signal to be bandlimited and incorporate the jitter via a stochastic model. Next, we derive an approximate model based on a first-order Taylor series and use an... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively