Sharif Digital Repository

Solid State Drives (SSDs) have recently emerged as a high speed random access alternative to classical magnetic disks. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-flash standards to respond to ever increasing application demands. In this paper, we first give a deep look at how different flash parameters and SSD internal designs affect the actual performance and scalability of the conventional architecture. Our experiments show that SSD performance improvement... 

In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs... 

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed... 

Cúk Converter operating in discontinuous capacitor voltage mode is an inherent PFC converter in which, unity power factor can be achieved using constant duty cycle and switching frequency. In this paper, a reduced-order switch network modeling technique is applied to Cúk converter operating in DCVM in order to derive small-signal model of the converter assuming a dc voltage source as the input source of the converter. This model is extended to derive the small-signal behavior of the converter while operating as a PFC converter. The validity of the proposed model is confirmed by both simulation and experimental results. Afterwards, a new control strategy is proposed in which switching... 

This paper presents a high performance Direct Torque Control (DTC) theme for the induction motor using Indirect Matrix Converter (IMC). To improve the dynamic behavior of motor, Active Learning Method (ALM) is implemented on the DTC. The ALM uses its own modeling technique called the ink drop spread (IDS) method. Functionally the IMC is very similar to the Direct Matrix Converter (DMC) but it has separate line and load bridges. In the inverter stage, the classical DTC method is employed. In the rectifier stage, in order to reduce losses caused by snubber circuit the rectifier four-step commutation method is employed. By suitably selecting switching pattern and using Active Learning Method... 

Abstract Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time... 

In this paper, an FPGA-controlled fault tolerant back-to-back converter for DFIG-based wind energy conversion application is studied. Before an open-circuit failure in one of the semiconductors, the fault tolerant converter operates as a conventional back-to-back six-leg one. After the fault occurrence in one of the switches, the converter will continue its operation with the remaining five healthy legs. Design, implementation, simulation and experimental verification of a reconfigurable control strategy for the fault tolerant six/five leg converter used in wind energy conversion are discussed. The proposed reconfigurable control strategy allows the uninterrupted operation of the converter... 

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA - a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short... 

This paper proposes a design technique for the implementation of a class-EM power amplifier (PA). Class- EM mode of operation has been proposed as an improved version of class-E in terms of efficiency and power gain, provided that the current fall time of switch is an appreciable portion of a period; the frequency of operation is high enough that the switching time of transistor can no longer be considered instantaneous. A novel approach for harmonic injection required for class-EM operation is proposed, followed by the system of equations and the design methodology governing the proposed circuit. As a proof of concept and verification of the proposed design method, a class-EM PA is designed... 

Conventional back-to-back converters with input power factor correction are still the best solution for motor drive applications which are usually subjected to considerable load changes during their operation. Since converter components, especially input-side inductances are designed for nominal power rating, the rated input power factor and input current distortion aren't achievable in light loads. In this paper a control method is proposed to improve the input current distortion and input power factor in light loads. This is achieved by increasing the switching frequency according to the reduction in load. Since conduction and switching losses decrease in light loads, the overall losses by... 

The commutation issue is the most important limiting factor of expanding AC chopper applications, which in most cases are solved by employing snubber circuits, implementing sensor-based selective switching patterns and utilising resonant circuits. To overcome the commutation problem, this study proposes a novel non-resonant AC/AC buck converter with no snubber circuits and no sensor-based switching patterns. The introduced hardware configuration and the proposed control strategy provide a path for an inductive load current in all switching states. This converter offers higher reliability and efficiency as well as lower cost compared to the AC choppers with snubber circuits or voltage and... 

Server workloads operate on large volumes of data. As a result, processors executing these workloads encounter frequent L1-D misses. In a many-core processor, an L1-D miss causes a request packet to be sent to an LLC slice and a response packet to be sent back to the L1-D, which results in high overhead. While prior work targeted response packets, this work focuses on accelerating the request packets. Unlike aggressive OoO cores, simpler cores used in many-core processors cannot hide the latency of L1-D request packets. We observe that LLC slices that serve L1-D misses are strongly temporally correlated. Taking advantage of this observation, we design a simple and accurate predictor. Upon... 

Performance of a data center is a function of three features; bandwidth, latency, and reliability. By adopting optical technology in data center network, bandwidth increment, in addition to reduction of transmission latency and power consumption, is achieved. Unfortunately, fault tolerance of the optical networks has raised less attention so far. So in this paper, we propose a fault-tolerant, scalable, and high-performance optical architecture built upon previously proposed O-TF network, with the goal of redundancy optimization and reducing the minimum number of wavelength channels required for non-blocking functionality of the network. Moreover, reducing network diameter, in O-FTF network... 

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM.... 

Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18um CMOS technology in ADS environment show the... 

Data center performance is affected by three main factors; bandwidth, latency, and reliability of intra-data center interconnection network. Bandwidth and latency are definitely improved by adopting optical technology for intra-data center communication, but fault tolerance of the corresponding optical networks has been raised less. Recently, we introduced two Torus-based, all-optical, and non-blocking networks, i.e. O-TF and O-FTF, addressing reliability of optical networks, and now, in this paper, to address the scalability problem, we propose a novel Optical Clos-based architecture which reduces minimum number of required wavelength channels, as well as, the switch size in each node....