Speculative Path Setup for Fast Data Delivery in Server Processors

Please enable javascript in your browser.

Bakhshalipour, Mohammad | 2017

1894 Viewed

Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 49976 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Sarbazi-Azad, Hamid; Lotfi-Kamran, Pejman
Abstract:
Server workloads operate on large volumes of data. As a result, processors executing these workloads encounter frequent L1-D misses. An L1-D miss causes a request packet to be sent to an LLC slice and a response packet to be sent back to the L1-D, which results in high overhead. While prior work targeted response packets, this work focuses on accelerating the request packets through a simple-yet-eﬀective predictor. Upon the occurrence of an L1-D miss, the predictor identiﬁes the LLC slice that will serve the next L1-D miss and a circuit will be set up for the upcoming miss request to accelerate its transmission. When the upcoming miss occurs, the resulting request can use the already established circuit for transmission to the LLC slice. We show that the proposal outperforms data prefetching mechanisms while requiring signiﬁcantly less overhead. Using full-system simulation, we show that the proposed method accelerates serving data misses by 22% and leads to 10% performance improvement
Keywords:
Multicore Processors ; Circuit Switching ; Data Prefetching ; Network-on-Chip (NOC) ; Data Miss ; Server Processors