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cmos-technologies
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Design and Implementation of Protected Smart High Side and Low Side Switch and Drivers in 0.18um HV BCD CMOS Technology
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Zolghadri, Mohammad Reza (Supervisor)
Abstract
In this thesis, two types of smart switch & driver chips are designed in 0.18 um HV BCD technology; low side driver and high side driver. These drivers are smart, because of having various types of protection and detection circuits, which protect switch, driver and connected load, versus errors that can be occurred by the user or other environmental effects. The protection circuits are battery over & under voltage shutdown, current limit, inductive load clamper and thermal shutdown. Load status is checked by status detection circuit and reported to user by one bit flag. Battery voltage can vary from 7 V to 40 V and output current is limited to 2 A. Designed high side and low side drivers are...
Design and Fabrication of Buck-Boost DC-DC Converter and Linear Regulator With Digitally-Tunable Output Voltage in 0.18µm-HV BCD CMOS Process
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor)
Abstract
In this project, an inverting Buck-Boost converter with two negative linear regulator is designed, implemented and measured in CMOS 0.18μm-HV BCD technology. Input voltage of Buck-Boost converter can vary from +15V to +28 and output voltage is digitally adjustable from -1V to -10V. Maximum output current of the converter is 300mA. A current mode controller and a lag compensator is used to control the converter. A high speed highside current sensor is designed and used in current mode controller. Sampled current of the current sensor is also used in a current limit circuitary to limit the maximum current of highside switch. Two negative linear regulators are placed at the output of the...
Design and Implementation of Local Interconnect Network (LIN)Transceiver in High Voltage BCD 0.18 um
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Faez, Ramin (Supervisor)
Abstract
In this study, a Local Interconnect Network (LIN) transceiver was designed and implemented. This chip contains transmitter, receiver, low power receiver, digital control unit, oscillator, voltage regulator, high voltage switch, temperature sensor and battery voltage detector. The main focus on this study was on designing transmitter,receiver, low power receiver and temperature sensor. Through designing of this chip, in addition to functional and physical layer specification that mentioned in ISO 17987, electromagnetic compatibility specifications have been considered significantly.The designed chip with slope control and wave shaping of BUS signal has excellent radiated emission performance....
Design of A Digitally Controlled Bias Chip For A Transceiver
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Sheikhaei, Samad (Supervisor)
Abstract
Advances in IC fabrication makes possible have systems on chips. In this thesis we have designed and fabricated a digitally controlled bias chip for a transceiver which can be programmed by its digital interface. In this thesis, briefly we review basics of voltage regulators and methods for controlling them. Then we introduce high voltage 0.18um CMOS technology. In this thesis, we describe the requirements of a specific transceiver and present a system to overcome these requirements. This system has positive, negative and internal regulators, a five-bit analog to digital converter, temperature sensors, power amplifier controller and digital serial interface. In this thesis, we present a...
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology
, Article International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN) ; Atarodi, S. M ; Luong, H. C ; Sharif University of Technology
Wiley
2012
Abstract
This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including...
A bridge technique for memristor state programming
, Article International Journal of Electronics ; Volume 107, Issue 6 , 2020 , Pages 1015-1030 ; Maymandi Nejad, M ; Haghzad Klidbary, S ; Bagheri Shouraki, S ; Sharif University of Technology
Taylor and Francis Ltd
2020
Abstract
In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is...
CMOS integrated delay chain for X-Ku band applications
, Article Analog Integrated Circuits and Signal Processing ; Volume 102, Issue 1 , 2020 , Pages 213-224 ; Daryabari, F ; Medi, A ; Sharif University of Technology
Springer
2020
Abstract
A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 μ m CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from...
A 5.3ps 8b Time to digital converter using a new gain-reconfigurable time amplifier
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; 2018 ; 15497747 (ISSN) ; Hajsadeghi, K. H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE
Design of a 2-12-GHz bidirectional distributed amplifier in a 0.18- mu m CMOS technology
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 2 , 2019 , Pages 754-764 ; 00189480 (ISSN) ; Meghdadi, M ; Yaghoobi, M ; Medi, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- boldsymbol mu ext{m} CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ( n-{ ext {opt}} ), maximum achievable power gain ( G-{P} ), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n ) is offered where dc-power consumption of the circuit ( P-{ ext {dc}} ) is also considered. This formula optimizes G-{P}/P-{ ext {dc}} , and it is preferred over the conventional n-{ ext {opt}} formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB...
A 5.3-ps, 8-b time to digital converter using a new gain-reconfigurable time amplifier
, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 66, Issue 3 , 2019 , Pages 352-356 ; 15497747 (ISSN) ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
Time amplifiers (TAs) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18- μm CMOS technology. Using a supply voltage of 1.2 V, the proposed TDC consumes 1.1 mW at 30 MS/s throughput. © 2004-2012...
Novel trombone topology for wideband true-time-delay implementation
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 68, Issue 4 , 2020 , Pages 1542-1552 ; Medi, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2020
Abstract
A novel trombone topology has been introduced for achieving controllable true time delay. The prominent aspect of the proposed topology is the ability to provide discrete variable delay with minimum insertion loss variation with delay settings. Furthermore, the effects of source impedance, output load, and line-terminating loads' impedance mismatch on group delay variation are theoretically investigated for the proposed trombone topology. Moreover, based on this new topology, a prototype trombone delay circuit has been designed and fabricated in 0.18- mu ext{m} CMOS technology, operating over the frequency bandwidth of 8-18 GHz. This 3-bit delay integrated circuit provides a maximum delay...
High precision CMOS integrated delay chain for X-Ku band applications
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 68, Issue 4 , 2020 , Pages 1553-1563 ; Medi, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2020
Abstract
A high-precision delay chain circuit integrated in a 0.18- mu ext{m} CMOS technology working in the frequency bandwidth of 8-18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay...
A low power 25 MS/S 12-bit pipelined analog to digital converter for wireless applications
, Article 2003 Southwest Symposium on Mixed-Signal Design, SSMSD 2003, 23 February 2003 through 25 February 2003 ; 2003 , Pages 38-42 ; 0780377788 (ISBN); 9780780377783 (ISBN) ; Mehrmanesh, S ; Vahidfar, M. B ; Safarian, A. Q ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2003
Abstract
A 12 bit 25 MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 μm CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve requirements of 12 bit resolution and settling in 20 ns within 0.05% accuracy. However, pipeline ADCs are tolerant to comparator's offset, but using dynamic comparators, power dissipation can be reduced. So a dynamic comparator is designed which is more power efficient. Total power dissipation is about 76 mW from a single 3 V supply, where INL and DNL are 0.8 LSB and 0.6 LSB respectively. A SNDR of 70.1 dB is achieved. © 2003 IEEE
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using 'Slew boost' technique
, Article 2003 International Symposium on Low Power Electronics and Design, ISLPED 2003, 25 August 2003 through 27 August 2003 ; Volume 2003-January , 2003 , Pages 340-344 ; 15334678 (ISSN); 158113682X (ISBN) ; Mehrmanesh, S ; Vahidfar, M. B ; Safarian, A. Q ; Lotfi, R ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2003
Abstract
An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM
A 1.5-V supply, 10.7-MHz, bandpass gm-C filter in a 0.6μm standard CMOS technology
, Article 14th International Conference on Microelectronics, ICM 2002, 11 December 2002 through 13 December 2002 ; Volume 2002-January , 2002 , Pages 46-49 ; 0780375734 (ISBN) ; Atarodi, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2002
Abstract
A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6μm standard CMOS process is designed. The THD of the transconductor for a 0.7Vpp input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70μm current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage. © 2002 IEEE
A 1.8V high dynamic range CMOS Gm-c filter for portable video systems
, Article 14th International Conference on Microelectronics, ICM 2002, 11 December 2002 through 13 December 2002 ; Volume 2002-January , 2002 , Pages 38-41 ; 0780375734 (ISBN) ; Aslanzadeh, H. A ; Vahidfar, M. B ; Atarodi, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2002
Abstract
A 4th order, 5 MHz, lowpass Butterworth Gm-c filter has been combined with a low noise low-voltage amplifier to form a lowpass filter for video applications. In this filter an improved transconductor and a powerful method is used to adjust the transconductance gain for tuning application. A continuous variable gain current-to-current converter is used to tune the transconductor value. The THD of the filter is -77 dB for 1 Vppd input signal. Input referred noise is 40 nV/√Hz in the worst case. All the circuits are designed based on a 0.25 μm CMOS process technology with a single 1.8 V supply. © 2002 IEEE
PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era
, Article IEEE Transactions on Computers ; Volume 66, Issue 6 , 2017 , Pages 982-995 ; 00189340 (ISSN) ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
IEEE Computer Society
2017
Abstract
Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of...
A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology
, Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier Ltd
2019
Abstract
A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The...
Energy consumption analysis of the stepwise adiabatic circuits
, Article Microelectronics Journal ; Volume 104 , October , 2020 ; Saeidi, R ; Sharif University of Technology
Elsevier Ltd
2020
Abstract
In this paper, an analytic model of the energy consumption of the Stepwise Adiabatic Circuits (SAC) when it is possible to discharge the load capacitor is proposed. Using this model, analytical derivations are calculated which shows us the power saving of the SACs. Using analytical derivations, the sizing of a capacitor tank is determined for a desired energy saving. For example, the derivations predict that if the sizing of the 3-step series tank capacitors is equal to the load capacitor, the power saving is 55%. Also, if the sizing of the tank is very large the energy saving of a 3-step stepwise charging is equal to 66.7%. Several Simulations in 0.18μm CMOS technology prove the accuracy of...
A 7 bit, 3 GHz bandwidth random-time-interleaved-hybrid DAC using a novel self-healing structure for DCE in 65 nm CMOS technology
, Article AEU - International Journal of Electronics and Communications ; Volume 134 , 2021 ; 14348411 (ISSN) ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
Elsevier GmbH
2021
Abstract
The application of time-interleaved structure leads to new amplitude and time errors while reducing many static and dynamic errors. In this case, both amplitude and time error are decreased by circuit structures integrated into a 7-bit DAC. In the present study, a new structure was proposed based on the randomization of two-interleaved paths in order to reduce the amplitude error, which can be extended to the N-channels-interleaved. In order to reduce the cycle-duty-error, a self-correction structure based on calculating the amplitude of the error before and measuring the time of this error along with the passage of the main signal through the output multiplexer is provided. The advantage of...