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    Design of Low Phase Noise DCO in All Digital Frequency Synthesizers

    , M.Sc. Thesis Sharif University of Technology Bagherzadeh Sohrabi, Salar (Author) ; Atarodi, Mojtaba (Supervisor)
    Abstract
    A new class of design has been introduced in the RF circuits and Frequency Synthesizers, which is based on the digital circuits. Implementation of the digital synthesizers suppresses the need to use loop filter and thus reduces the loop lock time. In this thesis different topologies of digitally controlled oscillators using inductor and capacitor tank and all digital architectures used in high frequency all digital synthesizers in 0.18um CMOS technology has been inspected and simulated. Novel techniques introduced to improve the ring oscillator-based design’s specifications which doesn’t need inductor. Using the introduced techniques, the phase noise has been lessened acceptably with respect... 

    , M.Sc. Thesis Sharif University of Technology Miraki, Mohammad (Author) ; Sharif Khani, Mohammad (Supervisor)
    Abstract
    With the advancement of the technology, Design of low power devices such as biomedical systems, wireless sensor network, portable devices and … has received more attention. Digitally controlled oscillator (DCO) is one of the sub-blocks in systems such as all digital phase locked loop (ADPLL) which consumes the major power of the system. Therefore, Design of a low power DCO will decrease the power consumption of the system significantly.
    In this thesis, a digital control oscillator which is ultra low power is design for system on chip applications. Coarse-Fine architecture is used with binary weighted cells in this design. For the Coarse tuning stage, a new delay cell is proposed which... 

    A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology

    , Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) Heydarzadeh, S ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
    Elsevier Ltd  2019
    Abstract
    A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The...