Sharif Digital Repository

The integration of high-voltage direct-current (dc) transmission lines in conventional alternating-current (ac) systems would affect the indirect measurement of phasor measurement unit (PMU) devices since the concept of phasors would not correspond to dc transmission circuits. The optimal PMU placement problem in ac/dc systems subjected to the system observability is presented in this paper by applying a mixed-integer programming model. In practice, the cost of each PMU is variable as a function of PMU measurement channels. This attribute is incorporated in the proposed model as well. In addition, the number of PMU measurement channels is deemed to be technically limited; thus, the common... 

Demand response (DR) as a state-of-the-art program is accommodated in the energy efficiency contexts of the smart grid. Lack of the customer knowledge about how to respond to the time-differentiated tariffs and offered controlling signals is the major obstacle in the way of broad DR implementing. As a solution, an optimization method, namely load control (LC), is proposed to automatically control the on/off status of the responsive appliances in a smart home. This paper focuses on the direct load control (DLC) program in the category of incentive-based DR programs. LC is extended to consider inconvenience cost of the DLC implementation for DLC program participants. Outputs of the extended LC... 

This paper enhances the observability of power networks by taking into consideration random component outages. The architecture of wide-area measurement system (WAMS) is analyzed in order to identify components that would affect the network observability. An iterative framework is devised to calculate a bus index in power networks equipped with phasor measurement units (PMUs) and conventional measurements. The average of bus indices represents a system index which provides an overall insight on the power network observability. The system index is utilized as a criterion to distinguish among multiple optimal PMU placements. Conventional bus injection and line flow measurements and the effect... 

In this paper, a model for the optimal placement of contingency-constrained phasor measurement units (PMUs) in electric power networks is presented. The conventional complete observability of power networks is first formulated and then, different contingency conditions in power networks including measurement losses and line outages are added to the main model. The communication constraints which would limit the maximum number of measurements associated with each installed PMU is considered as measurement limitations. The relevant formulations are also proposed to make the model more comprehensive. The IEEE standard test systems are examined for the applicability of proposed model. The... 

In recent years, there has been a growing interest in the simulation and analysis of piezoelectric transducers with the he help of equivalent electrical circuit simulations (EECS). This paper has been devoted to study of such approach for two designed and fabricated ultrasonic sandwich transducers. By using analytical analysis, the dimensions of components of the two piezoelectric transducers were determined for the assumed resonance frequencies of 30 kHz and 40 kHz. Then, by using a two dimensional finite element model, and regarding two different modeling techniques for the transducers and by application of a current source which was connected directly to the piezoelectric pieces of the... 

Current and force calculations in different short-circuit conditions are required for short-circuit performance analysis of a multi-winding traction transformer which is one of the most important requirements in its design process. This paper extends the available low-frequency three-winding star equivalent circuits to develop a novel equivalent circuit for the four-winding traction transformers. The leakage inductances of the traction transformer are determined and employed to calculate the parameters of this developed star model. It is shown that the star equivalent circuit is a valid and appropriate model to simulate the steady-state and dynamic performance of the traction transformer... 

This paper reports on design and measurement results of a state of the art low-noise and high-gain transimpedance amplifier (TIA) implemented in 0.18 μm TSMC CMOS technology. Thorough design methodology for high gain and low power TIA design for 2.5 Gb/s optical communication circuits family is presented. A noiseless capacitive feedback is proposed and implemented as a noise efficient feedback network for TIA circuits. Besides, analytical noise calculations in this family of TIA circuits are presented and optimum noise criteria are derived. The saturation and instability problem of TIA circuits resulted from DC dark current of the input photodiodes (PDs) is addressed and a circuit level... 

This study proposes a spiking neuro-fuzzy clustering system based on a novel spike encoding scheme and a compatible learning algorithm. In this system, we utilize an analog to binary encoding scheme that properly maps the concept of "distance" in multi-dimensional analog spaces to the concept of "dissimilarity " of binary bits in the equivalent binary spaces. When this scheme is combined with a novel binary to spike encoding scheme and a proper learning algorithm is applied, a powerful clustering algorithm is produced. This algorithm creates flexible fuzzy clusters in its analog input space and modifies their shapes to different convex shapes during the learning process. This system has... 

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits' combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection... 

Demand response (DR) as a state-of-the-art program is accommodated in the energy efficiency contexts of the smart grid. Lack of the customer knowledge about how to respond to the time-differentiated tariffs and offered controlling signals is the major obstacle in the way of broad DR implementing. As a solution, an optimization method, namely load control (LC), is proposed to automatically control the on/off status of the responsive appliances in a smart home. This paper focuses on the direct load control (DLC) program in the category of incentive-based DR programs. LC is extended to consider inconvenience cost of the DLC implementation for DLC program participants. Outputs of the extended LC... 

Fault diagnosis following a disturbance in a power system is of great importance for the operators in the control center as a prerequisite for system restoration. In this article, for the first time, an analytic method for fault diagnosis, using the wide area measurement system (WAMS) and employing circuit rules, is developed. Instead of conventional information about status of protective relays and circuit breakers, voltage and current phasors at different points of the power network after fault occurrence are utilized. Because most of the power systems will be equipped with WAMS consisting of high-speed sampling features, the proposed method introduces a new application of WAMS for fault... 

New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in class-AB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18μm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method  

Reliability analysis of combinational logic circuits using error probabilities methods, such as PTM, has been widely developed and used in literature. However, using these methods for reliability analysis of sequential logic circuits will lead to inaccurate results, because of existence of loops in their architecture. In this paper a new method is proposed based on converting the sequential circuit to a secondary combinational circuit and applying an iterative reliability analysis to the resulting configuration. Experimental results demonstrate good accuracy levels for this method  

Lattice Reduction (LR) has been proposed as a method to enhance the performance of MIMO detectors such as ZF, MMSE and V-BLAST. Until recently, the application of LR to the superior K-Best tree-search detection algorithm was not practical due to the significant increase in complexity of K-Best as a result of the distortion of tree symmetry caused by LR. However, in our recently published work we developed an innovative K-Best algorithm to accommodate tree-asymmetry with no additional complexity. In this work, we build on this result and perform a detailed analysis of the effect of various LR algorithms on the performance of LR-aided K-Best. We show that LLL and Seysen provide equivalent... 

A new modeling and analysis of the nonlinearities caused by the capacitor mismatch errors in the pipeline analog-to-digital converters (ADCs) is presented. Error in each stage is modeled by an input-referred gain error and a nonlinear term. A method is proposed for calculation of the ADC integral nonlinearity (INL) from the total input referred error. Analytical expressions for estimation of the ADC INL in terms of standard deviation of random capacitor mismatch errors are derived. The proposed model is verified by system-level Monte Carlo simulations  

Bode stability analysis based on transmission line modeling (TLM) for single wall carbon nanotube (SWCNT) interconnects used in 3D-VLSI circuits is investigated for the first time. In this analysis, the dependence of the degree of relative stability for SWCNT interconnects on the geometry of each tube has been acquired. It is shown that, increasing the length and diameter of each tube, SWCNT interconnects become more stable  

This paper enhances the observability of power networks by taking into consideration random component outages. The architecture of wide-area measurement system (WAMS) is analyzed in order to identify components that would affect the network observability. An iterative framework is devised to calculate a bus index in power networks equipped with phasor measurement units (PMUs) and conventional measurements. The average of bus indices represents a system index which provides an overall insight on the power network observability. The system index is utilized as a criterion to distinguish among multiple optimal PMU placements. Conventional bus injection and line flow measurements and the effect... 

An important application of 3-D integration technology is stacked processor-DRAM systems. One of the major design issues in 3-D processor-DRAM stacks is power delivery. Presence of hot spots, high density power regions, in processor die poses serious challenges to the design of power distribution network (PDN). In this paper, we investigate solutions to ensure power integrity in the hot spot regions  

Robust performance controller design for duty-cycle controlled series resonant converter is proposed in this paper. The uncertainties of the converter are analyzed with load variation and power circuit components tolerances are taken into consideration. Additionally, a nominal performance H ∞ controller is designed. Closed-loop system is simulated and simulation results of robust controller are compared with H∞ nominal performance controller  

In parallel with enhancements in the technology of integrated circuits, transistors are implemented in silicon. Though the price is reduced; design is more complicated, which create the efficiency and power consumption. The reason why modern GDI-based circuit is the focus of attention is that in designing digital circuit, less power is required while more efficiency is obtained. Lowering the complexity of logic circuit can bring about reduction of power consumption, propagation delay and decrease circuit space. GDI-based integrated circuit resembles MOSFET transistors but have fewer transistors and higher performance capability. This study addresses two main areas which are Studying and...