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error-detection
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Including Facilities in an Embedded Processor for External Watchdog Processors
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghassem (Supervisor)
Abstract
The wide range of embedded processors and their reliance on nano-scale technologyhave brought them serious concerns on reliability, power consumption, timeliness and cost. Therefore, theseconcernsmust be addressed at the design process withemploying minimum facilities.This thesis proposes a low-cost concurrent error detection method based on control flow checking suitable for embedded processors. Most of the previous control flow checking methods either do not consider the embedded processors concerns, or they are not applicable to processors with on-chip cache memories.The key idea behind the proposed control flow checking method is to embed specific hardware components in the IP core of an...
Exception Fault Localization in Smart Mobile Applications
, M.Sc. Thesis Sharif University of Technology ; Heydarnoori, Abbas (Supervisor)
Abstract
In software programs, most of the time, there is a chance of error, even though they are tested carefully. Finding error-related pieces of code is one of the most complicated tasks and it can make incorrect results if done manually. Semi-automated and fully-automated methods have been introduced to overcome this issue. The rapid growth of developing smart mobile applications (SMAs) in recent years, competition among the development teams and many other factors have increased the chance of errors and hence, the quality of these applications have reduced. There are two approaches to test SMAs in order to reach a high degree of quality: (1) using existing traditional methods and adapting them...
Development Object Oriented Framework for Data Reconciliation of Chemical Processes
, M.Sc. Thesis Sharif University of Technology ; Bozorgmehry Boozarjomehry, Ramin (Supervisor)
Abstract
In this study, in order to enhance data contaminated with random and gross errors, the implementation of data reconciliation technique on large-scale industrial unit was investigated. Data reconciliation results on the naphtha reformer unit, revealed that uncertainty in estimation of input and output reactor temperatures, decreased up to 2% in comparison with measured ones. In addition, uncertainties in estimation of the mass flow rates have declined by nearly 30%. Also, an object-oriented framework for plant wide data reconciliation was designed. This framework was designed as an extension of plant wide identification software developed previously. Moreover, adding five classes to the...
Design and Implementation of Decoder and Encoder for Error Detecting and Correcting Algorithms for RF Links in Networks on Chip
, M.Sc. Thesis Sharif University of Technology ; Hesabi, Shaahin (Supervisor)
Abstract
In the upward trend of advancing technologies in chips manufacturing, utilizing Network on Chip (NOC) solutions is a sensible approach towards overcoming challenges in System on Chip (SOC). The most common form of NOC is the Wired NOC. The continuous physical size reduction of electronic circuits has led to bandwidth deficiency as well as increased temperature in various parts of these circuits. The vast advancement in chips manufacturing industry has made it possible to embed and adapt telecommunication equipment into chips, giving rise to Wireless NOC (WNOC) manufacturing. However, wireless communication increases fault rate; thereby, the system becomes more vulnerable against transient...
Evaluating the Energy Consumption of Fault-Detection Mechanisms in Embedded Systems
, M.Sc. Thesis Sharif University of Technology ; Ejlali, Alireza (Supervisor)
Abstract
Memories are one of the main component in the embedded systems, and owing to their vulnerability to error, this part of system must be fault tolerant. Single error correction (SEC) codes are one of the most commonly used methods against sot errors. However, on the other hands as the technology scales, multiple bit upsets (MBUs) are becoming more likely to occur in the memories and the SEC codes have lost their effectiveness in fault coverage. Therefore a greater attention is devoted to the codes with the higher fault coverage such as single error correction/double error detection (SEC/DED) codes. These codes increase the delay, area and power consumption overhead. These parameters are the...
Hardware Trojan detection and localization based on local detectors
, Article Turkish Journal of Electrical Engineering and Computer Sciences ; Volume 26, Issue 3 , 2018 , Pages 1403-1416 ; 13000632 (ISSN) ; Manzuri Shalmani, M. T ; Hemmatyar, A. M. A ; Sharif University of Technology
Turkiye Klinikleri Journal of Medical Sciences
2018
Abstract
Hardware Trojans are one of the serious threats with detrimental, irreparable effects on the functionality, security, and performance of digital integrated circuits. It is difficult to detect Trojans because of their diversity in size and performance. While the majority of current methods focus on Trojan detection during chip testing, run-time techniques can be employed to gain unique advantages. This paper proposes a method based on the online scalable detection technique, which eliminates the need for a reference chip. Involving local detectors, this technique assesses the variations in the logical values of each node to find out whether there are Trojans. This method excludes time and...
Plant-wide simulation model for modified claus process based on simultaneous data reconciliation and parameter estimation
, Article Chemical Engineering Transactions ; Volume 57 , 2017 , Pages 997-1002 ; 22839216 (ISSN); 9788895608488 (ISBN) ; Rad, A ; Sharif University of Technology
Italian Association of Chemical Engineering - AIDIC
2017
Abstract
The modified Claus process is characterized by several problems, namely poor instrumentation and no precise kinetic model for predicting the behaviour of the reactors. Using operational data of an industrial plant, this paper proposes a general framework for development of a plant-wide simulation model for modified Claus process based on simultaneous data reconciliation and parameter estimation (DRPE) using Genetic algorithm (GA). HYSYS as a commercial process simulator that provides a high-level of accuracy as well as redundancy which all is favoured for DRPE has been utilized in this work. Building a communication framework between HYSYS and MATLAB, data pre-processing of raw measurement...
Categorization of various essential datasets and methods for textual spelling detection and normalization
, Article Iranian Journal of Information Processing Management ; Volume 32, Issue 4 , 2017 , Pages 1143-1170 ; 22518223 (ISSN) ; Abdi Ghavidel, H ; Sharif University of Technology
Iranian Research Institute for Scientific Information and Documentation
2017
Abstract
One of the most primary phases of automatic text processing is spelling error detection and grapheme normalization. Storing textual documents faces several problems without passing this phase, which causes a disturbance in retrieving the documents automatically. Therefore, specialists in the fields of natural language processing and computational linguistics usually make an attempt to sample various data through presenting ideal methods and algorithms in order to reach the normalized data. Several researches have been conducted on English and some other languages, which have been followed by a certain amount of researches on Farsi too. Sometimes, these several researches have remained to be...
Low energy yet reliable data communication scheme for network-on-chip
, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 34, Issue 12 , 2015 , Pages 1892-1904 ; 02780070 (ISSN) ; Palesi, M ; Eskandari, S ; Hessabi, S ; Afzali-Kusha, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
In this paper, a low energy yet reliable communication scheme for network-on-chip is suggested. To reduce the communication energy consumption, we invoke low-swing signals for transmitting data, as well as data encoding techniques, for minimizing both self and coupling switching capacitance activity factors. To maintain the communication reliability of communication at low-voltage swing, an error control coding (ECC) technique is exploited. The decision about end-To-end or hop-To-hop ECC schemes and the proper number of detectable errors are determined through high-level mathematical analysis on the energy and reliability characteristics of the techniques. Based on the analysis, the extended...
Joint detector & estimator design for widely separated MIMO radars
, Article 2016 IEEE Radar Methods and Systems Workshop, RMSW 2016 - Proceedings, 27 September 2016 through 28 September 2016 ; 2016 , Pages 136-140 ; 9781509010493 (ISBN) ; Nayebi, M. M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
This paper considers the detector design and performance analysis in a widely separated multiple input - multiple output (S-MIMO) radar. We studied this subject under some assumptions such as single point target, Swerling models for radar cross section and Gaussian interference. The target is moving in piecewise linear trajectory and multi-scan data is stored. So, the target cell maybe changed through the time. A GLRT detector is derived that employs all data at once in a central unit. The performance of detector is extracted and numerical simulations verify all results
A cache-assisted scratchpad memory for multiple-bit-error correction
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 24, Issue 11 , 2016 , Pages 3296-3309 ; 10638210 (ISSN) ; Sadat Mirzadeh, N ; Farhady Ghalaty, N ; Miremadi, S. G ; Fazeli, M ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Scratchpad memory (SPM) is widely used in modern embedded processors to overcome the limitations of cache memory. The high vulnerability of SPM to soft errors, however, limits its usage in safety-critical applications. This paper proposes an efficient fault-tolerant scheme, called cache-assisted duplicated SPM (CADS), to protect SPM against soft errors. The main aim of CADS is to utilize cache memory to provide a replica for SPM lines. Using cache memory, CADS is able to guarantee a full duplication of all SPM lines. We also further enhance the proposed scheme by presenting buffered CADS (BCADS) that significantly improves the CADS energy efficiency. BCADS is compared with two well-known...
A new noise-immune method to detect protective CT saturation and its release instants
, Article 2016 IEEE International Conference on Power and Renewable Energy, ICPRE 2016, 21 October 2016 through 23 October 2016 ; 2017 , Pages 284-287 ; 9781509030682 (ISBN) ; Vakilian, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2017
Abstract
CT saturation is a phenomenon that can cause inaccurate fault current measurement and may result in related protective relay failure to block the high current flow under a fault condition in a power system. Hence, it is required to develop a method to detect occurrence of CT saturation with a good accuracy under presence of noise in a power system. In this paper, a new method having the afore-mentioned characteristics is presented. The main benefit of exploiting the introduced approach here for detecting CT saturation is its high level of reliability as well as its reasonable operational speed in CT saturation detection. In other words, these two properties are implemented to this method....
Design and analysis of optimum distribution free OS-CFAR for non coherent radars
, Article International Radar Symposium, IRS 2005, 6 September 2005 through 8 September 2005 ; Volume 2005-January , 2005 ; 21555753 (ISSN) ; Sheikhi, A ; Nayebi, M. M ; DLR; EADS; serco - bringing service to life; sms GmbH; Technische Universitat Hamburg-Harburg (TUHH) ; Sharif University of Technology
IEEE Computer Society
2005
Abstract
In this paper, general form of optimum distribution free (D.F.) detector for noncoherent radars is extracted. This general form is very complex to be analyzed, therefore, we have derived two special cases and one case which is more interesting and practical is analyzed accurately. We have shown that in spite of its simple form, the detector has considerable benefits over conventional OSCFAR schemes
A novel video temporal error concealment algorithm based on moment invariants
, Article 9th Iranian Conference on Machine Vision and Image Processing, 18 November 2015 through 19 November 2015 ; Volume 2016-February , 2015 , Pages 20-23 ; 21666776 (ISSN) ; 9781467385398 (ISBN) ; Ghanei Yakhdan, H ; Kasaei, S ; Sharif University of Technology
IEEE Computer Society
Abstract
Nowadays, the use of multimedia services such as video sequences is constantly growing. Unfortunately, due to the lack of reliable communication channels and video data sensitivity to transmission errors, the quality of received video might decrease. Therefore, decoder error concealment methods have been developed to retrieve the damaged or lost data. In this paper, a novel temporal error concealment (TEC) algorithm based on moment invariants is presented. It includes three main stages of: designation of candidate motion vectors (MVs) set, adaptive determination of block size in the current and reference frames for feature extraction, and error function calculation based on moment...
Memory mapped SPM: Protecting instruction scratchpad memory in embedded systems against soft errors
, Article Proceedings - 9th European Dependable Computing Conference, EDCC 2012 ; 2012 , Pages 218-226 ; 9780769546711 (ISBN) ; Fazeli, M ; Khosravi, F ; Miremadi, S. G ; Sharif University of Technology
IEEE
2012
Abstract
Predictability, energy consumption, area and reliability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories play an increasing role to satisfy these concerns. Both cache and SPM as on-chip SRAM memories are highly vulnerable to soft errors and as they contain the most frequently used blocks of the program, their errors can easily propagate in system leading to erroneous results. Unlike the instruction cache, an error in the instruction SPM cannot be corrected using only parity bits by invalidating the erroneous line. This study suggests a low-cost mechanism to protect the instruction SPM against soft errors. The main idea underlying the...
A fully analog calibration technique for phase and gain mismatches in image-reject receivers
, Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 5 , May , 2015 , Pages 823-835 ; 14348411 (ISSN) ; Kananian, S ; Fotowat Ahmady, A ; Sharif University of Technology
Elsevier GmbH
2015
Abstract
A systematic approach to I/Q mismatch calibration in image-reject receivers is presented in this paper. A new error detection algorithm is proposed, which automatically calibrates for phase and gain mismatches limiting the performance of image-reject receivers. A dual-loop feedback is employed which looks for the minimum phase/gain error using a 2-dimensional analog-based search algorithm and then finds the minimum value for the error. An experimental CMOS prototype RF front-end for cognitive radio applications operating at 400-800 MHz is proposed and simulated in the 0.18 μm CMOS technology, achieving an image rejection ratio (IRR) better than 55-dB in post-layout simulation. The...
Axial position detection for optical tweezers based on Moiré Deflectometry
, Article Optics Communications ; Volume 446 , 2019 , Pages 33-38 ; 00304018 (ISSN) ; S. Reihani, S. N ; Sharif University of Technology
Elsevier B.V
2019
Abstract
Optical tweezers are indispensable instruments for applying and measuring Pico-Newton range forces. The magnitude of the exerted force is determined by measuring the displacement of the trapped bead from the center of the trap. Recently, we developed a new detection system for optical tweezers based on Moiré Deflectometry (MD). In this work, we show, both theoretically and experimentally, that the introduced method can be used for detection in the axial direction, as well, with a significantly larger sensitivity compared to the commonly used QPD method. As an example, for a 2.17μm polystyrene bead this method could provide a sensitivity 285% larger than that of the QPD method. © 2019...
Phase-change memory architectures
, Article Advances in Computers ; Volume 118 , 2020 , Pages 29-48 ; Sarbazi Azad, H ; Sharif University of Technology
Academic Press Inc
2020
Abstract
Some of the recent approaches regarding leverage PCM will be reviewed in this chapter. The chapter starts with a discussion regarding future main memory systems that includes hybrid architecture schemes using both PCM and DRAM arrays. Later, we focus on PCM only approaches and this section will help describe some techniques for reducing the increased read latency because of slow writes in PCMs. In this chapter, we also illustrate wear-leveling approaches and review the security problems of this memory approach which are lifetime limited. This section includes an overview of the recent security aware wear-leveling techniques, whose methods help detect attacks, and their issues during the...
Fault-resilient lightweight cryptographic block ciphers for secure embedded systems
, Article IEEE Embedded Systems Letters ; Vol. 6, issue. 4 , 2014 , pp. 89-92 ; ISSN: 19430663 ; Tian, K ; Azarderakhsh, R ; Bayat Sarmadi, S ; Sharif University of Technology
Abstract
The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches...
PSP-Cache: A low-cost fault-tolerant cache memory architecture
, Article Proceedings -Design, Automation and Test in Europe, DATE ; 2014 ; ISSN: 15301591 ; ISBN: 9783981537024 ; Miremadi, S. G ; Sharif University of Technology
Abstract
Cache memories constitute a large fraction of processor chip area and are highly vulnerable to soft errors caused by energetic particles. To protect these memories, most of the modern processors employ Error Detection Codes (EDCs) or Error Correction Codes (ECCs). EDCs/ECCs impose significant overheads in terms of area and energy; these overheads increase as a function of interleaving EDCs/ECCs to detect/correct multiple errors. This paper proposes a new cache architecture to minimize the area and energy overheads of EDCs/ECCs in set-associative L1-caches. Simulation results for a 4-way set-associative cache show that the proposed architecture reduces both the area and static power overheads...