Sharif Digital Repository

According to prediction of ITRS, power consumption and bandwidth of processors' interconnection, will be the most major bottleneck of the System-on- Chips (SoCs) in the future. Therefore, in MultiProcessor System-on-Chip (MPSoC) architectures, the design constraints will be altered from "Computational Constraints" to "Communicational Constraints". There are three kinds of communications in the surface of the chip: Global, median and local. The main difference between global and local connections is that the length of latter one will be changed with technology. In other words, it is scalable like processor's elements while the length of global connections is practically constant. Even though... 

Nowadays by increasing the number of processing cores in system-on-chip, using networks-on-chip, as an optimized interconnection foundation for transferring data between processing cores is inevitable .Based on this, the necessity of designing and implementing an optimized structure for testing network-on-chip, considering various overheads such as power consumption, latency, bandwidth and area, becomes an important issue in designing network-on-chip. The purpose of this project is to design an optimized structure for testing routers and connecting links in network, which considers power consumption overhead, latency and area overhead on one hand, and fault coverage on the other hand.... 

The exponential increase in power density within a chip due to higher frequency of operation in recent years (Moor's law) is a major limiting factor for designers. Increasing the number of parallel cores instead of increasing the frequency of operation is a possible solution. The design of connections within the cores can be followed by the old process but the global interconnectsbetween the cores instead of point to point can be replaced byNetwork-on-Chip (NoC). In this thesis, The dimensions of global interconnects in many-core chips are optimized for maximum bandwidth density and minimum delay taking into account network-on-chip router latency and size effects of coppe. The optimal... 

The shrinkage of feature sizes has resulted in global wiring delays being the bottleneck in on-chip interconnects. As a consequence, Network-on-Chip (NoC) emerged as a desirable interconnect structure between Processing Elements (PEs) on a chip. On the other hand, due to the non-uniform communication patterns among PEs, it is beneficial for the routers input ports to have a reconfigurable buffer structure. Having this in mind, we proposed a reconfigurable microarchitecture for on-chip routers which is able to reconfigure the Virtual Channels (VCs) in input ports, without lowering the clock frequency of the router. For this purpose, we presented a simple and efficient mechanism for monitoring... 

Software Defined Networking (SDN) provides a logically centralized view of the state of the network, and as a result opens up new ways to manage and monitor networks. In this dissertation a novel approach to network intrusion detection in SDNs is introduced that takes advantage of these attributes. This approach can detect compromised routers that produce faulty messages, copy or steal traffic or maliciously drop certain types of packets. To identify these attacks and the affected switches, we correlate the forwarding state of network---i.e. installed forwarding rules---with the forwarding status of packets---i.e. the actual route packets take in the network and detect anomaly in routes.... 

With the expansion of network equipment including routers and wireless modems, these equipment have become more susceptible to backdoors and hacker attacks. One way to cause troubles to these systems is through backdoor insertion. Recently, several attacks via backdoor insertions have been reported by some of the major router companies. In this project, a complete description of routers, ways of intrusion to routers and how to change settings in routers in order to measure traffic intensity are explained. In this thesis we manually setup a backdoor in a router in order to observe its effects on local networks. Furthermore, we purposely attack a router in order to find the followings: 1. Ways... 

There is a plethora of research and implementations that intend to increase the performance and reduce implementation costs of network routers. In this work, we review previous designs and propose a new network router design that is based on software-defined networks. Our design separates the data plane and the control plane from each other and connects both parts by using OpenFlow protocol. The control plane consists of a general small computer that utilizes the Quagga software to enforce the routing protocols. The control plane translates routing decisions to OpenFlow instructions and sends them to the data plane. The data plane is based on a switch that supports the OpenFlow protocol... 

The advancement of technology in the semiconductor industry and the resulting increase in the number of transistors on a chip has led to an increase in the number of processing cores an increase in the number of processing cores in a system on chip (SoC). A surge in the number of processing cores, makes their communication more and more noteworthy. This communication is established through the network on chip (NoC). One of the main challenges in NoC design is power management, as it constitutes a high percentage of the overall power consumption of the chip. One of the most power-hungry components of NoC is the router. According to our observation, some of the components of the routers are...