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Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories due to their lower leakage power consumption. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system. We present a predictable non-volatile data memory for real-time embedded systems which improves both worst-case execution time... 

Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories instead of conventional SRAM due to their lower leakage power consumption and smaller cell area. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems to resume their execution without a large startup delay. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system if not managed... 

Recently, the tradeoff between low energy consumption and high fault-tolerance has attracted a lot of attention as a key issue in the design of real-time systems. Dynamic Voltage Scaling (DVS) is commonly employed as one of the most effective low energy techniques for real-time systems. It has been observed that the use of feedback-based methods can improve the effectiveness of DVS-enabled systems. In this paper, we have investigated reducing the energy consumption of fault-tolerant hard real-time systems using the feedback control theory. Our proposed method makes the system capable of selecting the proper frequency and voltage settings in order to reduce the energy consumption, while... 

In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably... 

Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems. Many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories. However, accessing these memories imposes performance and energy overhead and using them as the code memory could increase the worst case execution time of the system. In this paper, a new code memory architecture for non-volatile memories is proposed which reduces the effective memory access latency by employing memory access interleaving technique. Unlike common instruction access latency improvement techniques such as prefetching and... 

This article introduces an architecture exploration tool to study and understand the tradeoffs of future processor systems using nonvolatile memory and help guide the design of the future. Energy efficiency serves as a critical factor in designing embedded systems. Furthermore, the growing dominance of energy harvesting systems (EHSs) in sensor-rich applications has eventuated an emerging trend in wearable-systems and IoT devices as an alternative to battery-powered embedded systems. In this article, researchers have presented CATNAP-Sim, a simulator for EHSs, with NVP and hybrid NVM-SRAM memory  

Worst case execution time and energy consumption are two of the most important design constraints of real-time embedded systems and memory subsystem has a major impact on both of them. Therefore, many recent studies have tried to improve the memory subsystem of embedded systems by using emerging non-volatile memories instead of conventional memories such as SRAM and DRAM. Indeed, the low leakage power dissipation and improved density of emerging non-volatile memories make them prime candidates for replacing the conventional memories. However, accessing these memories imposes performance and energy overhead and using them as the instruction memory could increase the worst case execution time,... 

Energy consumption is a major challenge in IoT devices, which was aimed to be improved by employing energy-efficient objective functions (OFs) in the structure of the RPL routing protocol. Meanwhile, the majority of the existing OFs mainly perform the parent selection based on the gathered information from the routing layer. Nevertheless, based on our investigations, there exists a series of transmission operations in the medium access control (MAC) layer, which significantly affects the energy consumption in IoT devices. Therefore, in this article, we propose ELITE, an energy-efficient cross-layer OF, which introduces a novel routing metric, called strobe per packet ratio (SPR). SPR... 

Energy harvesters are used in today's Wireless Sensor Networks (WSNs) to harvest energy from the environment. Although an energy harvester can provide a supply source with a much greater lifetime than a battery, the amount of available energy for an energy harvesting system is a random variable. Furthermore, the proper management of energy harvesters has a considerable impact on reliability. It has been observed that cooperative error control mechanisms like Cooperative Automatic Repeat Request (C-ARQ) and Cooperative Hybrid ARQ (C-HARQ) can be used for improving the energy management and reliability in Energy Harvesting WSNs (EH-WSNs). Recently, the impact of C-ARC mechanism has been... 

Two important objectives in wireless sensor networks are reliability and reducing energy consumption. Hence, overcoming energy constraints and utilizing error control schemes such as Automatic Repeat Request (ARQ) and Forward Error Correction (FEC) are necessary to improve the energy efficiency and reliability. However, these two concerns are at odds, so there is a trade-off between them. Considering this point, the impact of various error control schemes on these objectives and the trade-off between them has been considered in Bluetooth networks recently. However, all these works consider ideal assumptions (e.g., perfect error detection) only. This work evaluates the energy-efficiency of... 

Estimating the energy consumption of applications is a key aspect in optimizing embedded systems energy consumption. This paper proposes a simple yet accurate instruction-level energy estimation model for embedded systems. As a case study, the model parameters were determined for a commonly used ARM7TDMI-based microcontroller. The total energy includes the energy consumption of the processor core, Flash memory, memory controller, and SRAM. The model parameters are instructions opcode, number of shift operations, register bank bit flips, instructions weight and their Hamming distance, and different types of memory accesses. Also, the effect of pipeline stalls have been considered. In order to... 

To scavenge the energy from the environment and extend the network lifetime, some wireless sensor networks (WSNs) have been equipped with energy harvesters recently. However, the variable amount of environmental energy can affect the reliability of energy harvesting wireless sensor networks (EH-WSNs). In addition, data transmission over a wireless media is vulnerable. Hence, utilizing suitable error control schemes are necessary to improve the reliability. Regarding this point, Automatic Repeat Request (ARQ) and Cooperative ARQ (C-ARQ) schemes are applied in this generation of WSNs. Conventional ARQ as well as C-ARQ scheme are considered and examined through simulation. A comparative... 

Mixed-criticality systems are introduced due to industrial interest to integrate different types of functionalities with varying importance into a common and shared computing platform. Low-energy consumption is vital in mixed-criticality systems due to their ever-increasing computation requirements and the fact that they are mostly supplied with batteries. In case when high-criticality tasks overrun in such systems, low-criticality tasks can be whether ignored or degraded to assure high-criticality tasks timeliness. We propose a novel energy management method (called Stretch), which lowers the energy consumption of mixed-criticality systems with the cost of degrading service level of... 

Energy consumption is an important issue in designing embedded systems and the emerging Internet of Things (IoT). The use of non-volatile memories instead of SRAM in these systems improves their energy consumption since non-volatile memories consume much less leakage power and provide better capacity given the same die area as SRAM. However, this can impose significant performance overhead because the write operation latency of non-volatile memories is more than that of SRAM. In this paper we presented an NVM-based data memory architecture for embedded systems which improves the performance of the system at the cost of a slight energy consumption overhead. The architecture employs... 

Energy harvesting systems powered by renewable energy sources employ hybrid volatile-nonvolatile memory to enhance energy efficiency and forward progress. These systems have unreliable power sources and energy buffers with limited capacity, so they complete long-running applications across multiple power outages. However, a power outage might cause data inconsistency, because the data in nonvolatile memories are persistent, while the data in volatile memories are unsteady. State of the art studies proposed various memory architectures and compiler-based techniques to tackle the data inconsistency in these systems. These approaches impose too many unnecessary check-points on the system to... 

With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of... 

Given the importance of reducing energy consumption and the challenge of heat generation in classic CMOS circuits, adiabatic circuits are believed as an appropriate alternative. Most of the adiabatic circuit families come with a dual-rail structure, which provides them with an inherent hardware redundancy. Although this redundancy could be used for improving their reliability, no studies have been previously conducted to exploit this feature. In this regard, in this paper, we show that by exploiting the inherent hardware redundancy in adiabatic circuits, their reliability could be improved, while imposing a relatively low amount of energy overhead. Subsequently, with utilizing the outcome... 

Energy harvesting systems powered by renewable energy sources employ hybrid volatile-nonvolatile memory to enhance energy efficiency and forward progress. These systems have unreliable power sources and energy buffers with limited capacity, so they complete long-running applications across multiple power outages. However, a power outage might cause data inconsistency, because the data in nonvolatile memories are persistent, while the data in volatile memories are unsteady. State of the art studies proposed various memory architectures and compiler-based techniques to tackle the data inconsistency in these systems. These approaches impose too many unnecessary check-points on the system to... 

In this work, we address peak power and maximum temperature in multi-core Mixed-Criticality (MC) systems. In these systems, a rise in peak power consumption may generate more heat beyond the cooling capacity. Additionally, the reliability and timeliness of MC systems may be affected due to excessive temperature. Therefore, managing peak power consumption has become imperative in multi-core MC systems. In this regard, we propose an online peak power management heuristic for multi-core MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and Dynamic Voltage and Frequency Scaling (DVFS). Specifically, our... 

In modern multi-core Mixed-Criticality (MC) systems, a rise in peak power consumption due to parallel execution of tasks with maximum frequency, specially in the overload situation, may lead to thermal issues, which may affect the reliability and timeliness of MC systems. Therefore, managing peak power consumption has become imperative in multi-core MC systems. In this regard, we propose an online peak power and thermal management heuristic for multi-core MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and per-cluster Dynamic Voltage and Frequency Scaling (DVFS). Specifically, our approach examines...