Sharif Digital Repository

Internet of Things (IoT) devices have strict necessity for power consumption in order to achieve expected battery life. IoT nodes feature extreme power consumption range over 100 dB, between their operating modes. The main focus of this paper is to design and implement a high precision, high dynamic range, low power, and flexible power measurement system, which can be applied to different applications. The proposed system consists of a voltage regulating control loop, zero offset amplifiers, high precision analog to digital converters, and reference voltage. The proper operation of the proposed circuit are verified numerically with simulations and experimental measurements. The implemented... 

In the case that phased array systems are not capable of attenuating interferences, Radio Frequency (RF) front-ends and Analog Digital Converters (ADCs) with a large dynamic range are required to avoid saturation of the receiver. This leads to a higher power consumption. In this paper, employing N-path circuits in Mixer-First receivers, a novel method is introduced in which spatial and frequency blockers are eliminated right before entering the system on the antennas input. In fact using this technique, adjustable spatial notch filter and band-pass frequency filter are implemented to suppress spatial and frequency interferences. The proposed method enhances the robustness and effectiveness... 

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit... 

The digital radio receivers often have fast analog to digital converters delivering vast amount of data. However, in many cases, the signal of interest represents a small proportion of that bandwidth. A Digital Down Converter (DDC) is a filter that extracts the signal of interest from the incoming data stream. In this paper we first introduce an algorithm based on FFT which can be applied for simultaneous frequency shifting and decimating of Intermediate Frequency (IF) band signals, then a simplified iterative algorithm is suggested to improve the quality of reconstructed baseband signal. ©2007 IEEE  

Level Crossing (LC) Analog-to-Digital converters have been suggested as an asynchronous alternative to conventional schemes. It is our intention to improve the performance of these LC converters. In this paper, we also suggest alternative adaptive and multi-level adaptive LC schemes and use an iterative method to drastically improve the performance of LC converters. The impressive improvement of these schemes make LC converters a potential competitor to other conventional A/D converters such as Sigma Delta Modulators (SDM). ©2007 IEEE  

In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE  

Centralized and cloud computing-based network architectures are the promising tracks of future communication systems where a large scale compute power can be virtualized for various algorithms. These architectures rely on high-performance communication links between the base stations and the central computing systems. On the other hand, massive Multiple-Input Multiple-Output (MIMO) technology is a promising solution for base stations toward higher spectral efficiency. To reduce system complexity and energy consumption, 1-bit analog-to-digital converters (ADCs) are leveraged with the cost of lowering the signal quality. To recover the lost information, more sophisticated algorithms, like... 

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC... 

In Analog to Digital Converters, the sampled values are not necessarily sampled in the desired time. Sampling may occur before or after the desired time because of using non ideal converters; therefore the output signal of converters contains a noise related to this inexact sampling time. In this paper, signal to noise ratio according to practical sampling of continuous signal will be estimated. For this estimation, we have assumed the continuous signal as a band limited, zero-mean real signal which is wide sense stationary (wss). Sampling rate is also considered equal or more than Nyquist sampling rate. It will be concluded that what condition should be applied in order to have any... 

A low voltage high speed class AB op-amp with new structure is presented. The proposed op-amp has been designed to drive a large capacitive load as large as 10 pf dedicated for high-resolution high-speed pipelined analog to digital converters. Consuming comparatively low power about 6 mw, the proposed class AB op-amps has an output swing of 2.6 Vpp from a single supply of 1.5 volt. It has been observed that this op-amp can be suitable for a 1.5 volt 13-bit Pipelined A/D with sampling rate of 60 MS/S. This op-amp is to be fabricated in standard 0.18u CMOS technology  

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called "Slew Boost" is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10bit 150MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp using 0.18um CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than 1mW from a single supply of 1 volt