Sharif Digital Repository

This paper presents a circuit level soft error-tolerant-technique, called RRC (Robust Register Caching), for the register file of embedded processors. The basic idea behind the RRC is to effectively cache the most vulnerable registers in a small highly robust register cache built by circuit level SEU and SET protected memory cells. To decide which cache entry should be replaced, the average number of read operations during a register ACE time is used as a criterion to judge. In fact, the victim cache entry is one which has the maximum read count. To minimize the power overhead of the RRC, the clock gating technique is efficiently exploited for the main register file resulting in... 

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are... 

We propose a wideband circularly polarized antenna that consists of a metallic patch and some parasitically coupled elements mounted on a grounded dielectric-ferrite substrate. The metallic patch is fed by a proximity-coupled feed line placed between the ferrite and the dielectric layers. The parasitically coupled elements are included to improve the impedance bandwidth of antenna and are excited through the metallic patch. The antenna utilizes the resonant modes of the structure, which rotate only in the clockwise or counter-clockwise direction. A semi-Analytical solution based on the magnetic wall approximation shows that the resonance frequencies of the clock-and counter-clockwise... 

In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall/rise time on the impedance transformation behavior of N-path filters. In the ideal case, the N-path filter is supposed to provide a short-circuit to the ground for undesired frequency contents and an open-circuit for the desired signal so that it lies within the passband of the filter. It is shown that clock skew and finite clock fall/rise time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with... 

The effect of clock skew and duty-cycle on the performance of high-Q N-phase band-pass filters (BPFs) have been examined in this paper. Following a mathematical approach and using the analytical derivations carried out, the effects of such non-idealities as clock skew and duty-cycle error are determined in an N-path filter. It is analytically proved that image signals from all integer multiples of the clock signal, rather than just those at (1 ± kN) multiples of the clock signal, land atop the wanted RF spectrum. In a real world clock generator, with non-idealities in effect, filtering property and proper behavior of the filter is adversely affected. Finally, system level simulation along... 

A novel N-path filter using a complex impedance is designed to replace the frontend SAW filters in receivers with on-chip bandpass filters. It is demonstrated that the center frequency of the filter can be tuned solely by changing the value of some capacitances without the need to change the clock frequency. In addition, thanks to the use of smaller capacitors, the silicon area is reduced compared to similar designs. The high-Q bandpass filter is realized utilizing two gyrators and an arrangement of four baseband capacitors with NMOS switches, driven by 4-phase 25% duty cycle clock signals. This paper also analyzes the performance of the proposed filter against imperfections such as thermal... 

This article presents a very low-power clock and data recovery (CDR) circuit with 8 parallel channels achieving an aggregate data rate of 20 Gbps. A structural top-down design methodology has been applied to minimize the power dissipation while satisfying the required specifications for short-haul receivers. Implemented in a 0.18μm digital CMOS technology, total power dissipation is 70.2mW or 3.51mW/Gbps/Ch and each channel occupies 0.045 μm2 silicon area. © 2005 IEEE  

A low-power comparator is presented. pMOS transistors are used at the input of the preamplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough preamplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the preamplifier gain and decrease the input common mode of the latch to strongly turn on the pMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for preamplification and avoid excess power consumption. The... 

This paper presents a quadrature-clock generator based on a novel low-power ring oscillator with a wide frequency tuning range and low temperature variations. The proposed ring oscillator consists of two differential delay cells with a new controllable capacitive load of an MOS transistor. The wide tuning range is achieved due to transistor utilization in different regions and considering its resistance not to narrow down the frequency range. Delay cells are biased with a minimum possible value of a proportion to absolute temperature current to decrease frequency variations to temperature while the power consumption is kept low. The validation of the proposed methods is proved by circuit... 

A gated current-controlled oscillator (GCCO) based topology is used to implement a low-power multi-channel clock and data recovery (CDR) system in a 0.18um digital CMOS technology. A systematic approach is presented to design a reliable and low-power system based on the required specifications. Behavioral simulations are also used to estimate the achievable bit error rate (BER), jitter tolerance (JTOL), and frequency offset tolerance (FTOL) of the proposed CDR. Using a single 1.8V supply voltage, the proposed 20Gbps 8-channel CDR consumes only 70.2mW or 3.51mW/Channel/Gbps while occupies 0.045mm2 silicon area. Copyright 2005 ACM  

A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center... 

Aging has become a critical CMOS reliability issue in nanoscales. In general, the aging effect is exhibited as an increase in the delay of the combinational parts and robustness degradation of memory structures. To monitor the aging state of the combinational parts, this paper proposes an aging sensor that is combined with the flip-flops of a chip. The function of this sensor is based on monitoring the stability violation of the critical path output, before the rising edge of the clock signal. The precision of the proposed sensor is about 2.7 × of the most accurate previously presented aging sensors. This is achieved by almost 33% less area overhead compared with state-of-the-art aging... 

In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency oscillators because of their drawbacks so that it needs neither more effort to meet Electro-Magnetic Compatibility (EMC) and requirements nor extra hardware to implement DLLs. We have formally evaluated the meta-stability of our technique. This evaluation shows that our technique reliably... 

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm 2 QRD chip,... 

Elliptic curve cryptography (ECC) has received attention, because it can achieve the same security level as other asymmetric methods while using a key with smaller length. Although ECC is more efficient compared with other asymmetric methods, the fast computation of ECC is always desirable. In this paper, a fixed-base comb point multiplication method has been used to perform regular point multiplication. In addition, two low-complexity (LC) and low-latency (LL) architectures for the regular point multiplication using fixed-base comb method have been proposed. The point multiplication architectures have been implemented using field-programmable gate array and application-specific integrated... 

In this paper, a new all optical phase-locked loop (OPLL) is proposed and analyzed. The scheme relies on using two optical Kerr shutters to reveal the OPLL's error signal. The set of optical Kerr shutters and the subsequent low-speed photodetectors realize two nonlinear cross-correlations between the local clock pulse stream (called pump in Kerr shutter notations) and the time-shifted replicas of the incoming received data signal (called probe). The outputs of the cross-correlators are subtracted to form the error signal of the OPLL. We characterize the mathematical structure of the proposed OPLL and identify its two intrinsic sources of phase noise, namely, randomness of the received... 

The electric field of the modes of semiconductor microring lasers (SMRLs) in the presence of bus waveguide reflections are linear combinations of the clock wise (CW) and the counter clock wise (CCW) electric fields. The mode structures can be controlled by the waveguide reflection coefficients. The power ratio and phase difference of the CW and CCW fields of one mode is proportional to the ratio of the reflection coefficients of the left and right waveguides. It is shown that the degenerate CW and CCW modes in the presence of bus waveguide reflections are split into two modes with different frequencies. Employing these new modes, SMRL can be used as an element to design flip-flops used in... 

A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that... 

Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable in FPGA side of the proposed simulator, and the software side is implemented on an embedded soft-core processor. We transfer some parts of simulator, such as Traffic Generators (TGs) and Traffic Receptors (TRs), to software side without any degradation in simulation speed. Moreover, we...