Sharif Digital Repository

In this thesis, a brief review of the previously introduced all optical clock recovery methods are presented and then, two novel all optical PLLs, based on nonlinear Kerr effects in fiber optics, are introduced and thoroughly investigated. To obtain more insight into the subject, firstly, nonlinear Kerr effect and its two main applications, including FOPA amplifiers and optical Kerr shutters are described. One of the proposed PLLs employs a FOPA in its error signal detection process, and the other is based on using two Kerr shutter switches to detect the error signal. Since the PLLs are based on the quasi-instantaneous Kerr effect, they are expected to be suitable in ultra-high speed... 

Once a well has been drilled before it is cased with the steels (open-hole well), some logging must be done to record information’s about layers, geologic formations, geophysical and petrophysical properties of well. All the information’s that gathered from sensors and tools transmitted to the surface by a down-hole modem. This information is corrupted during the transmission by the communication channel. The most notable influence of this channel is noise, attenuation and interference between successive data bits. On the other hand, the characteristic of channel changes with the length of the cable, temperature, connections and so on. So using a set of fixed filters is not effective. The... 

In this thesis, A novel approach for ¼-rate clock Phase Detector (PD) structure for Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) is proposed. In this approach, the retimed data is generated within the circuit and no extra circuit is needed. Another advantage of this topology is that the error and reference signals are independent of delay time through gates and no extra replica circuit is needed to compensate the delay. This topology results in a lower power circuit and smaller area for high speed application compared to conventional topologies  

Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been... 

Some applications need fast locking clock and data recovery circuits for example the circuits that operate in burst mode must lock to the data packets which are transmitting from different transmitters very quickly and in just a few bit times. In such applications open-loop clock and data recovery circuits are used because lock time in closed-loop clock and data recovery circuits is usually much longer.
In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider... 

In this thesis, we statistically model and analyze one of the main systems in optical communications which are based on Second HarmonicGeneration (SHG) process. To this end, we first introduce various applications of this process in optical communication systems and see that the main application of this nonlinear process is in the process of optical clock recovery in both of OTDM and SPE_OCDMA networks. In the rest of the thesis, we characterize the mathematical structure of these systems and use that to statistically analyze their behavior. In considering the optical clock recovery system based on SHG, we introduce three intrinsic sources of timing jitter in the system, namely, the On-Off... 

The continuous growth of network traffic and people's demand for higher data rates, have driven wireline communication systems towards higher data rates. In these systems, the power consumption of these transmitters and receivers is a crucial and influential factor. This paper presents two different solutions to reduce the power consumption and area of these systems. In the first solution, a low-power phase shifter with variable phase and amplitude control is introduced. The changes in these parameters are mutually orthogonal, ensuring that a change in one characteristic does not affect the others. This phase shifter can be used to generate clock pulses with different phases in wireline... 

The Technology scaling and reduction of the size of transistors has led to an increase in the switching speed and, as a result, to an increase in the clock frequency.But in recent years, the continuation of this process of increasing the clock frequency has been almost stopped considering the considerations of power consumption. Previous research has shown that approximately 30-50% of the dynamic power consumed by the microprocessor is wasted in the clock distribution network.Therefore, the design of clock distribution networks is a big challenge for future microprocessors due to the trend of Technology scaling and process variation. In this thesis, we used the emerging technology of... 

Increasing demand for digital systems has led to developing signal processing in the digital domain. For this purpose, Analog to Digital Converters is used to convert analog signals to digital ones. Apart from that, by decreasing the size of transistors, it has been possible to implement the system on a chip that needs communication between analog and digital signals. The designed converter in this project is suitable for instrumentation purposes and especially for use in the control loop of a DC­DC digitally voltage converter. ADC architectures are mainly classified into two groups attributed with high bandwidth or with high resolution. Nature of on­chip measurement requires high... 

This project examines time in quantum mechanics, which includes three chapters. The first chapter is about clocks, which first deals with the history and invention of clocks, and then goes on to describe quantum clocks and various theories about them, including Perez and Faraday quantum clocks . The second chapter deals with the two-slit Yang experiments which, as in the preceding chapter, we first give a historical description of the experiment, and we will continue with our description. We consider that for each of these cases the probability of spatial and linear momentum interference is calculated. The third chapter is the final chapter. In this section, we first discuss the concept of...