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Design and Analysis of Low-Power VLSI Clock Distribution Networks, Considering Process Variations

Novin, Mohammad | 2023

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 56645 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sarvari, Reza
  7. Abstract:
  8. The Technology scaling and reduction of the size of transistors has led to an increase in the switching speed and, as a result, to an increase in the clock frequency.But in recent years, the continuation of this process of increasing the clock frequency has been almost stopped considering the considerations of power consumption. Previous research has shown that approximately 30-50% of the dynamic power consumed by the microprocessor is wasted in the clock distribution network.Therefore, the design of clock distribution networks is a big challenge for future microprocessors due to the trend of Technology scaling and process variation. In this thesis, we used the emerging technology of negative-capacitor field-effect transistors to make buffers, and with simulations, we showed that if these buffers are used to optimize the clock distribution network, simultaneously in a clock distribution network, compared to conventional CMOS technology , to have at least 70% power consumption and 7% less transmission delay time. Also, we examined the effects of variations in different parameters on the time propagation delay of the clock network, in the most important of which, for 10% changes in supply voltage, threshold voltage and channel length of transistors, NCFET network shows less variations than CMOS by 0.9, 3.6 and 12%, respectively. The effects of variations in different parameters of network wires have also been investigated, and in the worst possible case, for 5% variations in the length of network wires, the NCFET network experiences 2.6% more variations than CMOS ones. Due to the greater importance of the effect of temperature variations for the operation of electronic devices, we tested both networks in different temperature designs, and in the worst possible conditions, for the NCFET network, compared to CMOS, a maximum of 7% time delay variations and 0.5% more skew variations are observed. We tested and simulated the Effects of Crosstalk Noise for the designed clock network, and according to the investigated design, in the NCFET network, at least 7% delay and 10% less skew were observed compared to the competitors of CMOS networks
  9. Keywords:
  10. Low Power Consumption ; Cross Talk ; Delay Time ; Process Variation ; Clock Distribution Network ; Negative Capacitor Field Effect Transistors (NCFET) ; Time Propagation Delay ; Crosstalk Noise ; Very Large Scale Integration (VLSI)Circuits

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