Sharif Digital Repository

A compact, low power, clock frequency doubler circuit with no external devices designed and manufactured in a 0.5um CMOS technology. Proposed circuit generates a 4.096MHz output clock frequency from a 2.048MHz input clock while an automatic duty cycle control circuit reduces the sensitivity of the duty cycle of output clock to the duty cycle of input signal or process and temperature we variations. For this purpose, an accurate delayed clock is generated. structure besides MOSFET capacitors offers a impact and low power circuit. The area of the circuit is 0.08mm2 while consumes 380uArms SV power supply and drives 15pF capacitor load. Measured output duty cycle shows a variance of 2.7% from... 

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

This paper introduces a novel scalable pipelined VLSI architecture for a 4×4 64-QAM hard-output multiple-input-multiple-output (MIMO) detector based on K-best lattice decoders. The key contribution is a means of expanding the intermediate nodes of the search tree on-demand, rather than exhaustively, along with three types of distributed sorters operating in a pipelined structure. The proposed architecture has a fixed critical path independent of the constellation size, on-demand expansion scheme, efficient distributed sorters, and is scalable to higher number of antennas. Fabricated in 0.13 μCMOS, it occupies 0.95 μ mm} 2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW... 

A new family of sampled-data filters in which accuracy is a function of the ratio of the resistors is introduced. It is shown that this structure is suitable for low-voltage high-speed applications. A biquad filter with a quality factor of 10 and a clock frequency of 60MHz consuming only 2mW power is also presented  

A novel ultra high-throughput detection algorithm with an efficient VLSI architecture for high-order MIMO detectors in the complex constellations is proposed. The main contributions include a new method for the node generation in complex-domain, pipelinable sorters, and a simple combinational circuit instead of the conventional multipliers, which makes the proposed architecture multiplication-free. The proposed design achieves an SNR-independent throughput of 13.3 Gbps at the clock frequency of 556 MHz in a 0.13 μm CMOS technology with a near ML performance. The implemented design consumes 90 pJ per detected bit with the initial latency of 0.3 μs. Also, the synthesis results in a 90 nm CMOS... 

In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE