Loading...
Search for: cmos
0.005 seconds
Total 267 records

    Design and Implementation of Time and Frequency Synchronization in LTE

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 23, Issue 12 , January , 2015 , Pages 2970-2982 ; 10638210 (ISSN) Golnari, A ; Shabany, M ; Nezamalhosseini, A ; Gulak, G ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    A novel architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For symbol timing, we propose applying a symbol-folding method on top of the sign-bit reduction technique, leading to a novel algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated and compensated using an adaptive gain loop, which allows for a high-accuracy compensation in a short interval. In the frequency domain, for cell search, we propose a sign-bit reduction technique on top of the matched filter method for the primary synchronization signal detection. In addition, we... 

    A novel area-efficient VLSI architecture for recursion computation in LTE turbo decoders

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 62, Issue 6 , 2015 , Pages 568-572 ; 15497747 (ISSN) Ardakani, A ; Shabany, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are α and β recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing.... 

    A 38 pJ/b optimal soft-MIMO detector

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 64, Issue 9 , 2017 , Pages 1062-1066 ; 15497747 (ISSN) Shabany, M ; Doostnejad, R ; Mahdavi, M ; Gulak, P. G ; Sharif University of Technology
    Abstract
    An optimal soft multiple-input multiple-output (MIMO) detector is proposed with linear complexity for a general spatial multiplexing system with two transmitting symbols and NR 2 receiving antennas. The computational complexity of the proposed scheme is independent of the operating signal-to-noise ratio and grows linearly with the constellation order. It provides the soft maximum-likelihood solution using an efficient log-likelihood ratio calculation method, avoiding the exhaustive search on all the candidate nodes. Moreover, an efficient pipelined hardware implementation of the detection algorithm is proposed, which is fabricated and fully tested in a 130-nm CMOS technology. Operating at... 

    A novel tunable UWB pulse design for narrowband interference suppression implemented in BiCMOS technology

    , Article Proceedings - IEEE International Symposium on Circuits and Systems, 24 May 2009 through 27 May 2009, Taipei ; 2009 , Pages 405-408 ; 02714310 (ISSN); 9781424438280 (ISBN) Hedayati, H ; Fotowat Ahmady, A ; Sharif University of Technology
    2009
    Abstract
    The unique properties of modified Hermite pulses is utilized to develop a novel pulse technique for Ultra Wideband (UWB) communications. The proposed method increases the bandwidth of the pulse up to 10 GHz and overcomes the coexistence problem of UWB and vulnerable narrowband systems through suppressing narrowband interference. Consequently it improves the range of UWB communications by increasing the power, without disturbing the narrowband systems. The pulse technique is implemented in high frequency pulse generation circuits and could be fully integrated in BiCMOS process. The nulls of the frequency response are tuned to be located in a definite narrowband system with the number of the... 

    An analytical model for soft error critical charge of nanometric SRAMs

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 17, Issue 9 , 2009 , Pages 1187-1195 ; 10638210 (ISSN) Jahinuzzaman, S. M ; Sharifkhani, M ; Sachdev, M ; Sharif University of Technology
    2009
    Abstract
    Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus... 

    Full quantum mechanical simulation of a novel nanoscale DG-MOSFET: 2D NEGF approach

    , Article IEEE AFRICON 2007, Windhoek, 26 September 2007 through 28 September 2007 ; December , 2007 ; 142440987X (ISBN); 9781424409877 (ISBN) Dehdashti, N ; Orouji, A. A ; Faez, R ; Sharif University of Technology
    2007
    Abstract
    In this paper the electrical characteristics of a novel nanoscale double-gate MOSFET (DG-MOSFET) have been investigate by a full Quantum Mechanical simulation framework. This framework consists of Non-Equilibrium Green's Function (NEGF) solved self-consistently with Poisson's Equation. Quantum transport equations are solved in two-dimension (2-D) by recursive NEGF method in active area of the device to obtain the charge density and Poisson's equation is solved in entire domain of simulation to get potential profile. Once self-consistently achieved all parameters of interest (e.g. potential profile, charge density, DIBL, etc) can be measured. In this novel DG-MOSFET structure, a front gate... 

    The field effect transistor DNA biosensor based on ITO nanowires in label-free hepatitis B virus detecting compatible with CMOS technology

    , Article Biosensors and Bioelectronics ; Volume 105 , 15 May , 2018 , Pages 58-64 ; 09565663 (ISSN) Shariati, M ; Sharif University of Technology
    Elsevier Ltd  2018
    Abstract
    In this paper the field-effect transistor DNA biosensor for detecting hepatitis B virus (HBV) based on indium tin oxide nanowires (ITO NWs) in label free approach has been fabricated. Because of ITO nanowires intensive conductance and functional modified surface, the probe immobilization and target hybridization were increased strongly. The high resolution transmission electron microscopy (HRTEM) measurement showed that ITO nanowires were crystalline and less than 50 nm in diameter. The single-stranded hepatitis B virus DNA (SS-DNA) was immobilized as probe on the Au-modified nanowires. The DNA targets were measured in a linear concentration range from 1fM to 10 µM. The detection limit of...