Sharif Digital Repository

A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 μ m CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from... 

In order to effectively use a memristor in analog circuits, its memristance should be adjusted to a desired value between its limits. Since the maximum and minimum required memristance typically varies considerably between different types of memristors, it is almost impossible to tune the resistance of each memristor based on a reference resistor. Which is mostly done using some programmer circuits. Moreover, those programming strategies involving pulses are time-consuming and they impose high hardware headroom. In this paper, a novel CMOS circuit is presented for programming memristors. A Wheatstone bridge circuit is used to measure the current memristance, while the programming current is... 

This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis... 

A method for noise reduction in active-$RC$ circuits is introduced. It is shown that the output noise in an active-$RC$ circuit can be considerably reduced, without disturbing the circuit transfer function by inserting appropriate passive or active components in the circuit. The inserted components introduce new signal paths in the circuit for noise reduction while the original circuit transfer function is kept unchanged. The procedure to define the proper paths in the circuit and their transfer functions is given. The effectiveness of the presented method is demonstrated using a second-order active-RC filter fabricated in a 0.18-$ {m}$ CMOS technology  

An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS LC oscillator is discussed. The phase noise performance for this kind of oscillator is predicted by using a simplified model. This method enables us to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the presented method is demonstrated by designing an LC CMOS oscillator in a 0.24μm CMOS technology. The predictions obtained from the derived expressions are in good agreement with simulation results over a wide range of the supply voltage. © 2004 IEEE  

A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power  

An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first... 

In this paper, a fully integrated 30-dBm UHF band differential power amplifier (PA) with transformer-type combiner is designed and fabricated in a 0.18-μm CMOS technology. For the high power PA design, proposed transformer network and the number of power cells is fully analyzed and optimized to find inductors dimensions. In order to improve both the linear operating range and the power efficiency simultaneously, a parallel combination of the class AB and the class C amplifier in power cells was employed. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires  

A low-power wide-range CMOS temperature sensor architecture is proposed based on temperature-to-frequency conversion using supply voltage controlled sub-threshold ring oscillator. The principles of operation are investigated and proved via analytic and simulation results. Most errors are canceled out by this ratio-metric design. An inaccuracy of -0.84°C to +0.34°C occurs over a range of -40°C to 80°C after using a novel in-field digital two-point calibration. The entire sensor consumes less than 93nW to 305nW over the temperature range and can be digitally reconfigured for setting sample rate and resolution in a tradeoff  

A coplanar-fed wideband antenna array system to characterize MIMO channels in the 60 GHz band is proposed. The array consists of six U-slot patch elements with half-wavelength separation and is fed independently by individual transceivers. The system is designed and simulated on fused silica substrate to be integrated easily with RFICs and to achieve fine fabrication resolution (1um) for accurate mm-wave measurements. It can provide 11dBi peak gain at broadside and beam steering up to ±40° tilted from broadside over 57-63 GHz band. A new on-wafer calibration technique is developed to balance the amplitude and phase of all transceivers at the input of the array system which realizes high... 

In this paper, a fully integrated 900-MHz CMOS differential power amplifier (PA) with new power combiner is designed and fabricated in a 0.18- um technology. For the high power CMOS PA design, new transformer network and the number of power stages is fully analyzed and optimized to find inductors dimensions. A parallel combination of the Class AB and the Class C amplifier or multiple gated common source transistors in power stages was used to improve both the linear operating range and the power efficiency simultaneously. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires. Copyright © 2009 Praise... 

A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The... 

In this paper, capabilities of switched-current (SI) circuits are utilized to design a high-speed A/D converter. New methods to improve the performance of the SI circuits are introduced. An 8-bit 300MS/s pipeline ADC is design in 0.18um CMOS technology and an ENOB of 7.3b is obtained from simulations. The ADC consumes 40mW from a 1.8V supply. © 2007 IEEE  

An 8-bit High-speed folding/interpolating ADC is presented. Designed in 0.18μm CMOS technology, the ADC dissipates only 50mW from a single 1.5V supply. A novel technique based on using both N and P folding cells is used to widen the input range and a self-calibration technique based on using Trimmable MOSFETs is employed to improve the static and dynamic performance  

Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques  

A new, ultra low-voltage, linear CMOS OTA will be described. A 4th order, 18 MHz low pass Butterworth Gm-C filter has been designed with this new OTA stage for video applications. In this filter a new, fully digital approach has been used for frequency tuning. The THD of the filter for input signal 0.5 VPPis better than -60 dB. All of circuits are designed based on 0.25 um CMOS process technology with a single 1-volt power supply  

A low voltage high speed class AB op-amp with new structure is presented. The proposed op-amp has been designed to drive a large capacitive load as large as 10 pf dedicated for high-resolution high-speed pipelined analog to digital converters. Consuming comparatively low power about 6 mw, the proposed class AB op-amps has an output swing of 2.6 Vpp from a single supply of 1.5 volt. It has been observed that this op-amp can be suitable for a 1.5 volt 13-bit Pipelined A/D with sampling rate of 60 MS/S. This op-amp is to be fabricated in standard 0.18u CMOS technology