Sharif Digital Repository

In this paper, an 8-bit CMOS current-mode folding-interpolating ADC is presented. A new active averaging-interpolating network is described, which results in a better error correction factor compared to its resistive counterpart. Using novel circuits for fast settling and careful transistor sizing, a fast (>160 Msps) and low power (70 mW in 2.5 V supply voltage) 8-bit ADC, with a total chip area of 1 × 1.4 mm in a 0.25 micron CMOS process, is demonstrated. © Sharif University of Technology, April 2008  

A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps... 

This paper presents a simulation-based study of the stuck-open fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting stuck-open faults in these logic families. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented. © 2007 IEEE  

The application of time-interleaved structure leads to new amplitude and time errors while reducing many static and dynamic errors. In this case, both amplitude and time error are decreased by circuit structures integrated into a 7-bit DAC. In the present study, a new structure was proposed based on the randomization of two-interleaved paths in order to reduce the amplitude error, which can be extended to the N-channels-interleaved. In order to reduce the cycle-duty-error, a self-correction structure based on calculating the amplitude of the error before and measuring the time of this error along with the passage of the main signal through the output multiplexer is provided. The advantage of... 

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of... 

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a 0.18μm CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst... 

During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable... 

In this paper, we propose a new voltage controlled oscillator (VCO) with a high oscillation frequency yet low power consumption. The oscillator which is a single stage circuit has a low phase noise due to reduced noise sources. To evaluate the performance parameters, the oscillator was simulated in a 0.18-μm standard CMOS process. The results show that the oscillation frequency of VCO may vary between 4.66-5.9 GHz. Also, the phase noise of the VCO at oscillation frequency of 5.6 GHz is -99.7 dBc at 1 MHz offset frequency. Also, the power consumption was 4.8 mW at the same oscillation frequency. © 2007 IEEE  

A high speed, high resolution switched-current sample and hold (SI S/H) based on a new class AB transconductance stage is presented. Simulations performed on the SI S/H in standard 0.18um CMOS technology with 1.5v supply voltage indicate low power dissipation, high sampling speed and high SNR. © 2006 IEEE  

In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18μm CMOS process show a THD of less than 44dB for 0.6Vpp input signal and an input-referred noise of less than 45 nV/√Hz in worst case. The current consumption of each OTA is 1.5-mA. © 2006 IEEE  

An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE  

In this paper a new low-voltage two-stage class-AB line driver for ADSL applications is presented. The new proposed line-driver consists of only two stages with a new method to control the quiescent current of the output stage. The low-voltage full-CMOS high-linear line driver shows -77 dB THD for a load as low as 20 ohms. The line driver has variable gain, attenuating the input signal from 0dB to -14dB with 2dB steps. The peak to peak differential output swing is 4.2-V from a 2.5-V Supply voltage in a 0.25um standard CMOS technology  

A 1.8-v 13-bit 25MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.18um CMOS technology. The proposed new high speed low power class AB opamp makes it possible to achieve requirements of 13-bit resolution and settling in 12ns within 0.01% accuracy. An optimum architecture for noise and power consideration is also selected to reduce power. Total Power dissipation is about 82 mw from a single 1.8 v supply, where INL and DNL are 0.7 LSB and 0.6 LSB respectively. SNDR of 75.5 dB is achieved  

A 12 bit 25 MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 μm CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve requirements of 12 bit resolution and settling in 20 ns within 0.05% accuracy. However, pipeline ADCs are tolerant to comparator's offset, but using dynamic comparators, power dissipation can be reduced. So a dynamic comparator is designed which is more power efficient. Total power dissipation is about 76 mW from a single 3 V supply, where INL and DNL are 0.8 LSB and 0.6 LSB respectively. A SNDR of 70.1 dB is achieved. © 2003 IEEE  

This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including... 

A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. A new switched-network topology has been proposed for implementing the 5.625 ° phase shift step. The insertion loss of the circuit is compensated with an on-chip bidirectional amplifier. The measured return losses of the circuit are better than 8 dB with output 1-dB compression point of +9.5 dBm in the transmit mode and noise figure of 7.1 dB in the receive mode. The fabricated phase shifter demonstrates an average rms phase error of less than 2° over the entire operation bandwidth, which makes it suitable for high-precision applications  

In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD  

The leakage current and process variation are drastically increased with technology scaling. In Conventional SRAM cell due to process variations, stored data can be destroyed during read operation. Therefore, leakage current of SRAM cell and stability during read operation are two important parameters in nano-scaled CMOS technology. To overcome these limitations and to increase the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. The developed cell has six-transistors and uses two read/write-lines and two read/write-bit-lines during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The... 

To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode