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    Performance characterization of a low-cost dual-channel camera-based microarray scanner

    , Article 24th Iranian Conference on Electrical Engineering, ICEE 2016, 10 May 2016 through 12 May 2016 ; 2016 , Pages 1534-1538 ; 9781467387897 (ISBN) Akhoundi, F ; Ghobeh, M ; Ghiasvand, E ; Akbari Roshan, K ; Motahari, S. A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Abstract
    In this paper, we have proposed, designed, implemented, and characterized a low-cost camera-based microarray scanner which is capable of imaging fluorescently-labeled DNA or Protein microarrays. The proposed system is designed to simultaneously measure two different fluorescent dyes using two parallel channels which increase the overall scan speed. We have shown that the wide dynamic range of system makes it able to detect fluorophore densities from 100-106 molecule/μm2. In each capture, a 5.6 mm × 3.7 mm field is imaged on a 22.3 mm × 14.9 mm (18 megapixels) CMOS sensor. Therefore, the microarray can be scanned with ∼ 1μm2 spatial resolution which is high enough to distinguish borders of... 

    A tunable-Q 4-path bandpass filter with Gm-C second-order baseband impedances

    , Article 25th Iranian Conference on Electrical Engineering, ICEE 2017, 2 May 2017 through 4 May 2017 ; 2017 , Pages 244-248 ; 9781509059638 (ISBN) Rezvanitabar, A ; Babamir, S. M ; Behmanesh, B ; Atarodi, S. M ; Sharif University of Technology
    Abstract
    An active switched-capacitor 4-path bandpass filter suitable for multi-standard applications in ultra-high frequency (UHF) band with different channel bandwidths is designed and simulated in 0.18 μm CMOS technology. The baseband impedance of the filter is implemented as a second-order Gm-C low-pass filter which can be used to tune the channel bandwidth as well as the quality factor (Q) of the RF filter. The center frequency of the filter can be tuned from 100 MHz up to 1.5 GHz by changing the clock frequency applied to the filter while its bandwidth can be tuned by tuning impedance parameters in any center frequency. To do so, the baseband impedance utilizes a frequency dependent negative... 

    Floating bulk cascode class-e power amplifier

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; 2018 ; 15497747 (ISSN) Dehqan, A. R ; Toofan, S ; Lotfi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    In this paper, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the... 

    Floating bulk cascode Class-E power amplifier

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 66, Issue 4 , 2019 , Pages 537-541 ; 15497747 (ISSN) Dehqan, A. R ; Toofan, S ; Lotfi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    In this brief, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the... 

    High precision CMOS integrated delay chain for X-Ku band applications

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 68, Issue 4 , 2020 , Pages 1553-1563 Ghazizadeh, M. H ; Medi, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    A high-precision delay chain circuit integrated in a 0.18- mu ext{m} CMOS technology working in the frequency bandwidth of 8-18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay... 

    A new low voltage, high PSRR, CMOS bandgap voltage reference

    , Article 2008 IEEE International SOC Conference, SOCC, Newport Beach, CA, 17 September 2008 through 20 September 2008 ; 2008 , Pages 345-348 ; 9781424425969 (ISBN) Ashrafi, S. F ; Atarodi, M ; Chahardori, M ; Sharif University of Technology
    2008
    Abstract
    A new low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.18um CMOS technology, with a power supply of 1.4 volt. The results show PSRR is 65dB at 1MHz and the output voltage variation versus temperature (-40 to 140) is less than 0.1%. This circuit shows robustness against process variation. ©2008 IEEE  

    CNTFET full-adders for energy-efficient arithmetic applications

    , Article 6th International Conference on Computing, Communications and Networking Technologies, 13 July 2015 through 15 July 2015 ; 2015 ; 9781479979844 (ISBN) Grailoo, M ; Hashemi, M ; Haghshenas, K ; Rezaee, S ; Rapolu, S ; Nikoubin, T ; University of North Texas ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    Abstract
    In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm... 

    A 70 pJ/b configurable 64-QAM soft MIMO detector

    , Article Integration ; Volume 63 , 2018 , Pages 74-86 ; 01679260 (ISSN) Shabany, M ; Patel, D ; Milicevic, M ; Mahdavi, M ; Gulak, P. G ; Sharif University of Technology
    Elsevier B.V  2018
    Abstract
    An area and power efficient high-throughput VLSI implementation of a 4 × 4, 64-QAM soft multiple-input-multiple-output (MIMO) detector, that is suitable for high-order constellation schemes is presented. The proposed MIMO detector utilizes information contained in the discarded paths to improve the bit-error-rate (BER) performance, and then reduces computational complexity using three innovative improvement ideas. The proposed design is fabricated and fully tested in a 130 nm CMOS technology. Operating with a 270 MHz clock, the design achieves up to 655 Mbps throughput with 195 mW power dissipation at 1.32 V supply. Synthesis results in 65 nm CMOS technology shows that the proposed... 

    Design and Fabrication of Passive CMOS Phase Shifter

    , M.Sc. Thesis Sharif University of Technology Azizi Ghannad, Mehrdad (Author) ; Medi, Ali (Supervisor) ; Atarodi, Mojtaba (Co-Advisor)
    Abstract
    This research examines the issues of design and fabrication of Phase Shifter circuits on Silicon substrates. The Phase Shifter circuits are designed to have wide operation band width. They also should have very low sensitivity to process and temperature variation. A six bit phase shifter is designed at this research. We use a new topology for implementing the small phase shift steps and some circuits have been designed which their phase shifts can be adjusted after fabrication. All circuits are implemented with the 0.18µm CMOS technology. The research also explains all the necessary steps for measurement of fabricated circuits. The result of measurements shows good agreement with the... 

    Over 10-b On-Chip Impedance Measurement System for High Frequency Range

    , M.Sc. Thesis Sharif University of Technology Mirjalili, Ramin (Author) ; Atarodi, Mojtaba (Supervisor) ; Mehrani, Khashayar (Supervisor)
    Abstract
    Diabetes is one of the most catastrophic diseases in the world. There will be an end to patients’ problems if scientists can invent the artificial pancreas, but there is no implantable sensing core available. All of the sensors used for measuring blood glucose level were based on an electrochemical sensor which will generate a glucose level dependent electric current. The chemical structure of that sensor will deny its usability for in vivo applications. By exploring several biological and electrical literatures we introduced a fully electrical method for sensing the blood glucose level by impedance measurement. In this thesis we introduced a new method for sensing the blood glucose... 

    Frequency Domain HF on-chip Impedance Spectroscope with Over 10 bit Resolution

    , M.Sc. Thesis Sharif University of Technology Bakhshiani, Mehran (Author) ; Atarodi, Mojtaba (Supervisor) ; Mehrani, Khashayar (Supervisor)
    Abstract
    Impedance spectroscopy is known as one of the important integrated sensing methods in micro scale Biosensors and electrochemical sensors. Recently, Impedance spectroscopy has been noticed in many micro scale applications. These micro scale applications is being developed specially in bioelectronics and biomedical. The goal of this thesis is designing an on-chip impedance spectroscope system for high frequency with 10 bits resolution via fully electrical blood glucose concentration measurement. This system extracts the blood glucose concentration data through measuring the permittivity coefficient of blood at 1 GHz frequency. In this thesis, new method for high frequency high resolution... 

    Analysis of Digital DSP Blocks Using GDI Technology

    , M.Sc. Thesis Sharif University of Technology Faed, Mahdi (Author) ; Mortazavi, Mohammad (Supervisor)
    Abstract
    In line with developments in the technology of integrated circuits, transistors are implemented in silicon. Although the price is reduced; design is more complicated, which causes the efficiency and power consumption to face some difficulties in such design. The reason why modern GDI-based circuit is the focus of attention is that in designing a digital circuit, less power is required while more efficiency is obtained. Lowering the complexity of the logic circuit can bring about reduction of power consumption and propagation delay and decrease the circuit space. GDI-based integrated circuits resemble MOSFET transistors but have fewer transistors and higher performance capability. This study... 

    Design and Implementation of Ku-Band Variable Gain Amplifier in 0.18μm CMOS Technology

    , M.Sc. Thesis Sharif University of Technology Barzgari, Mohammad (Author) ; Medi, Ali (Supervisor)
    Abstract
    In this thesis, a Ku-band (16.3-17.3) Variable Gain Amplifier (VGA) for realizing a phase array T/R module is designed, implemented and measured in CMOS 0.18μm technology. In order to achieve a maximum gain of 15dB and NF of 4.3dB and with the idea of improving the 1-dB compression point, two gain-stages and a novel inter-stage is proposed according to pre-distortion method. Applying this linearizing technique, makes it possible to get output P-1dB higher than 18dBm. Current steering technique is used for gain control mechanism. Gain tunabality range of 31.5dB is needed and this forces 6-bit operation with 0.5dB gain-step for the VGA. Because of loading effect of higher bits on the lower... 

    Design and Implementation of X Band CMOS Vector Modulator

    , M.Sc. Thesis Sharif University of Technology Arjmandpour, Sina (Author) ; Medi, Ali (Supervisor) ; Kavehvash, Zahra (Supervisor)
    Abstract
    In this thesis, an X band vector modulator chip in CMOS .18 um technology is designed, implemented and measured. The receiver with two RF signal path includes differential amplifier, hybrid, attenuaters, variable gain amplifiers (VGA) and power combiner blocks respectively. Capability of gain and phase control is provided by 14 digital bit. 6 bits are used to control gain of each RF path, so that changing the phase and gain of the output signal in a trigonometric quarter shall be possible. The trigonometric quarter is selected by two single pole double throw switch. Cascode structure is utilized in amplifiers stages for its stability and isolation feature. Furthermore, in order to to enhance... 

    Design and Implementation of X-Ku Band Variable Gain Amplifier in CMOS Technology

    , M.Sc. Thesis Sharif University of Technology Shojaei, Mehdy (Author) ; Medi, Ali (Supervisor)
    Abstract
    In this thesis, a new wide band variable gain distributed amplifier (VGDA) is presented. A novel approach to implement uniform gain control in the wide band frequency range of 8 – 18 GHz is demonstrated. A different technique has been employed to provide necessary DC bias current, avoiding large DC-Feed inductors. A five-section wideband VGDA has been designed and fabricated in 0.18 μm CMOS technology. The VGDA have a flat gain of 11 dB, noise figure better than 5 dB, P1dB of 14 dBm at the output, input and output matching better than -12 dB and -14 dB, respectively, for maximum gain state over the 10 GHz UWB band. The gain control range is between 3 – 11 dB with gain steps of 0.5 dB and rms... 

    Design and Implementation of Fully Integrated Frequency Synthesizer for Biomedical Applications

    , M.Sc. Thesis Sharif University of Technology Aghlmand, Fatemeh (Author) ; Atarodi, Mojtaba (Supervisor)
    Abstract
    Fully integrated frequency synthesizer is one of the important system-on-chips building blocks. Among this circuit’s remarkable applications, Bioelectronics field is very common. In these applications, advanced microelectronic circuits are used in order to diagnosis and treatment of diseases. The aim of this thesis is design and implementation a wideband frequency synthesizer in a 0.18um CMOS technology. The main usage of this circuit is in a fully integrated implantable biomedical sensory chip. This circuit generates two necessary local signals in sensory chip to stimulus cells and process the information.
    Frequency synthesizer is based on phased locked loop (PLL) circuit and produce... 

    Design of a Low-power Receiver in Bluetooth Low-energy Standard

    , M.Sc. Thesis Sharif University of Technology Rahmanian Kooshkaki, Hossein (Author) ; Fotowat Ahmady, Ali (Supervisor)
    Abstract
    One of the most important parameters of a smartphone is the ability to operate in a long time with a rechargeable battery. As a result, the design of radio frequency circuits which are used in these cell phones is a consistent challenge for designers. Bluetooth Low-Energy standard (BLE) which is the fourth edition of Bluetooth standard is recently introduced with the aim of transporting low volume data with minimum power consumption. The most important challenge of the design of an RF receiver in the BLE standard is the power consumption. In a typical receiver, the oscillator and the mixer are the most power hungry blocks. Therefore, decreasing the power consumption of these two blocks is... 

    Analysis of PlasMOStor in CMOS Compatible Plasmonic Circuits

    , M.Sc. Thesis Sharif University of Technology Salehian, Borna (Author) ; Mehrany, Khashayar (Supervisor)
    Abstract
    Thus far numerous components and devices have been designed and realized based on plasmonics. Hereon, we focus on PlasMOStor which is probably the first and most important CMOS compatible plasmonic modulator. It resembles to its electronic counterpart MOS transistor in geometry, unless, it has a plasmonic waveguide instead of the regular channel to modulate optical signals . By applying voltage to the gate and inset of charge carrier accumulation, optical properties of the channel changes and plasMOStor turns off. In this thesis, we carry out a through investigation of plasMOStor’s operation. We show that the proposed theoretical description of plasMOStor is fallacious. Subsequently,... 

    A tunable high-Q active inductor with a feed forward noise reduction path

    , Article Scientia Iranica ; Volume 21, Issue 3 , 2014 , Pages 945-952 ; ISSN: 10263098 Moezzi, M ; Bakhtiar, M. S ; Sharif University of Technology
    Abstract
    The analysis and design of a tunable low noise active inductor is presented. The noise performance of the proposed gyrator-based active inductor is improved without either degrading its quality factor or consuming more power using a linear Feed Forward Path (FFP). The proposed low noise active inductor has been designed and fabricated using standard 0.18-μm CMOS technology. The measurements show a 3 fold improvement in the input noise current compared to that of conventional active inductors. The active inductor was tuned and measured at the resonance frequency of 2.5 GHz, which could be extended as high as 5.5 GHz, with a quality factor of 30. The circuit draws 4.8 mA from a 1.8 V supply  

    Two-dimensional multi-parameter adaptation of noise, linearity, and power consumption in wireless receivers

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Vol. 61, issue. 8 , July , 2014 , p. 2433-2443 Meghdadi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    Abstract
    This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,...