Sharif Digital Repository

A high-precision delay chain circuit integrated in a 0.18- mu ext{m} CMOS technology working in the frequency bandwidth of 8-18 GHz has been designed and tested. The designed delay control integrated circuit with 5-bit delay control provides a maximum delay of 125 ps and has a delay resolution of 3.9 ps. Measured delay error of the fabricated chip is less than 9.3%, making it a considerably accurate delay control circuit. Low delay-error performance has resulted from incorporating a novel delay cell in this delay chain circuit. This newly proposed delay cell is a lumped-element coupled transmission line loaded with a second-order all-pass network (APN). The APN-loaded coupled line delay... 

This paper presents a highly-linear transceiver core chip for X-band phased-array systems with two RX and one TX channels. Implemented in a standard 0.18-μm CMOS technology, the core chip provides 6-bit phase control (with rms error <2°) and 6-bit gain control (with rms error <0.6 dB) both within the 8.5–11.5 GHz frequency band. Improved accuracy is also available by digital calibration in narrowband applications. The receivers achieve a gain of 13.5 dB, an IIP3 of +10.3 dBm, and a noise figure of 8.2 dB, while drawing 170 mA per channel from the 3.3 V supply. The chip also provides an additional low-gain mode which further enhances IIP3 to +19.1 dBm and the input-referred P1dB to +11.4 dBm.... 

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during a read/write operation, only selected cell is connected to bit-line when one row is selected whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. Proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS... 

A new low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.18um CMOS technology, with a power supply of 1.4 volt. The results show PSRR is 65dB at 1MHz and the output voltage variation versus temperature (-40 to 140) is less than 0.1%. This circuit shows robustness against process variation. ©2008 IEEE  

A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power... 

This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter tolerance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is presented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 μm CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of... 

This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and... 

This paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded-cascode amplifier (FCA) results in 7× slew rate... 

Varactor frequency multipliers often show parametric instability with increasing RF input power. Examination of the added phase noise of the varactor frequency multipliers show that, if parametric oscillations are present in the circuit, output phase noise degrades remarkably in some specific driving levels. Phase noise analysis is done by the conversion matrix method. The conversion method predicts the phase noise degradation precisely because it encounters the noise conversion by large driving levels. The added phase noise of a varactor frequency doubler with subharmonic oscillation is calculated and the simulation results are compared with measurement results. Both simulation and... 

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with 0.18μ m CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the... 

This paper presents a new symmetric slew rate enhancement (SRE) circuit suitable for operational transconductance amplifiers (OTAs). The proposed SRE circuit is composed of two auxiliary circuits which are automatically activated during fast signal transitions (slewing) by comparing the input and output signals. The auxiliary circuits pump required current in/out the load capacitance. In this way, the slew rate of the amplifier is significantly improved without any extra static power dissipation. The proposed technique can be applied to a variety of operational amplifiers. However, incorporating the proposed SRE circuit into a folded-cascode amplifier (FCA) results in 7× slew rate... 

This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and... 

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a 0.18μm CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst... 

A novel architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For symbol timing, we propose applying a symbol-folding method on top of the sign-bit reduction technique, leading to a novel algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated and compensated using an adaptive gain loop, which allows for a high-accuracy compensation in a short interval. In the frequency domain, for cell search, we propose a sign-bit reduction technique on top of the matched filter method for the primary synchronization signal detection. In addition, we... 

Long-term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next-generation wireless communication systems. Turbo codes, the specified channel-coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple maximum a posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are α and β recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing.... 

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 n ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400-3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to... 

This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18μm CMOS technology and achieves 84dB dynamic range for a 10MHz signal bandwidth. Total analog power dissipation measured was 44mW  

In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm... 

An optimal soft multiple-input multiple-output (MIMO) detector is proposed with linear complexity for a general spatial multiplexing system with two transmitting symbols and NR 2 receiving antennas. The computational complexity of the proposed scheme is independent of the operating signal-to-noise ratio and grows linearly with the constellation order. It provides the soft maximum-likelihood solution using an efficient log-likelihood ratio calculation method, avoiding the exhaustive search on all the candidate nodes. Moreover, an efficient pipelined hardware implementation of the detection algorithm is proposed, which is fabricated and fully tested in a 130-nm CMOS technology. Operating at...