Sharif Digital Repository

A low power 4-bit flash ADC is proposed. A new power reduction technique is employed which deactivates the unused blocks in the converter structure in order to reduce the power consumption. A new method for built-in threshold voltage generation together with a new offset calibration method is used to further reduce the power consumption in the converter. Monte-Carlo simulation shows that after calibration both the INL and the DNL are lower than 0.35 LSB. The converter achieves 3.5 effective number of bits (ENOB) at 1.2 GS/s sampling rate after the offset calibration is performed. It consumes 10 mW from a 1.8 V supply, yielding a FoM of 560 fJ/conversion.step in a 0.18 μm standard CMOS... 

In this paper, a novel multiple antenna, high-resolution eigenvalue-based spectrum sensing algorithm based on the FFT of the received signal is introduced. The proposed platform overcomes the SNR wall problem in the conventional energy detection (ED) algorithm, enabling the detection of the weak signals at -10 dB SNR. Moreover, the utilization of FFT for the input signal channelization provides a simple, low-power design for a high-resolution spectrum sensing regime. A real-time, low-area, and low-power VLSI architecture is also developed for the algorithm, which is implemented in a 0.18 μm CMOS technology. The implemented design is the first eigenvalue-based detection (EBD) architecture... 

Long Term Evolution (LTE) supports peak data rates in excess of 300 Mb/s. A good approach to achieve such rates is by parallelizing the required processing in turbo decoders. An interleaver is an important part of a turbo decoder. LTE uses the Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for parallel decoding. In this paper, we propose an efficient architecture for the QPP interleaver, called the Add-Compare-Select (ACS) permuting network. A unique feature of the proposed architecture is that it can be used both as the interleaver and deinterleaver leading to a high-speed low-complexity hardware interleaver/deinterleaver for turbo decoding. The proposed design... 

As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When... 

A single chip UHF-RFID transceiver front-end is presented. The chip was designed according to EPCglobal Class-1 Gen-2 and supports both ETSI and FCC requirements. The receiver front end is capable of rejecting self-jammers as large as 10 dBm with the aid of a feedback loop. The stability and the robustness of the loop and other system requirements are studied. A 30 dBm class-AB power amplifier (PA) with 28% PAE is also integrated on the chip. The pseudo differential architecture of the PA greatly reduces the injection of the signal into the substrate. A simple model is used to estimate the effect of the substrate noise injection by the PA on the receiving circuit modules and design guides... 

With the emerging nanoscale CMOS technology, Multiple Event Transients (METs) originated from radiation strikes are expected to become more frequent than Single Event Transients (SETs). In this paper, a fast and accurate layout- based Soft Error Rate (SER) estimation technique with consideration of both SET and MET fault models is pro- posed. Unlike previous techniques in which the adjacent MET sites are obtained from logic-level netlist, we perform a comprehensive layout analysis to extract MET adjacent cells. It is shown that layout-based technique is the only effective solution for identification of adjacent cells as netlist-based techniques significantly underestimate the overall SER.... 

A novel detection algorithm with an efficient VLSI architecture featuring efficient operation over infinite complex lattices is proposed. The proposed design results in the highest throughput, the lowest latency, and the lowest energy compared to the complex-domain VLSI implementations to date. The main innovations are a novel complex-domain means of expanding/visiting the intermediate nodes of the search tree on demand, rather than exhaustively, as well as a new distributed sorting scheme to keep track of the best candidates at each search phase. Its support of unbounded infinite lattice decoding distinguishes the present method from previous K-Best strategies and also allows its complexity... 

A low power 4-bit, 1.6 GS/s flash ADC is presented. A new power reduction technique which masks the unused blocks in a semi-pipeline chain of latches and encoders is introduced. The proposed circuit determines the unused blocks based on a pre-sensing of the signal. Moreover, a reference voltage generator with very low static power dissipation is used. Novel techniques to reduce the sensitivity to dynamic noise are proposed to suppress the noise effects on the reference generator. The proposed circuit reduces the power consumption by 20 percent compared to the conventional structure when a Nyquist rate OFDM signal is applied. The INL and DNL of the converter are smaller than 0.3 LSB after... 

This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is... 

In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm 2 QRD chip,... 

An Eigenvalue-based detection (EBD) scheme, is proposed as an efficient method to overcome the noise uncertainty and the SNR wall problem in conventional energy detection (ED) schemes. Despite remarkable efforts made to analyze the EBD performance, a VLSI implementation is missing in literature. In this paper, a new FFT-based EBD algorithm is introduced, which eliminates the need for filter banks and discrete wavelet packet transform to channelize the input signal. The proposed method enables the utilization of the EBD algorithm in high-resolution spectrum sensing approaches. Moreover, it enables the detection of signals with SNRs as low as -10 dB. A low-power, area-efficient yet real-time... 

Cell search is a crucial process in the synchronization procedure for the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) system. In this paper, a high-speed, low-complexity and reliable architecture is proposed for both steps of cell search: sector ID and cell ID group detection. For the sector ID detection, two novel methods, sign-bit reduction and wise resource sharing, are proposed. In addition, for the cell ID group detection, we proposed an algorithm based on the Maximum Likelihood Sequence Detection (MLSD) called 'sign-bit MLSD'. Simulations show that the proposed methods result in more than 90% reduction in area compared to the state-of-the-art. We designed and... 

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using... 

The design strategy and efficiency optimization of UHF micro-power rectifiers using a novel diode connected MOS transistor is presented. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduce the threshold voltage and leakage current in compare to conventional diode connected transistors. Using the proposed diode in typical rectifiers makes a significant improvement in output voltage and current therefore the efficiency is increased comparing to the same rectifier architectures using conventional diodes. Also a design procedure for efficiency optimization is presented and a superposition method is used to optimize the performance of multiple output... 

A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center... 

A Multi-level asynchronous delta sigma modulator consist of several Schmitt-triggers and a novel time-to-digital converter is presented as a core of a delta sigma modulation based analog to digital converter (ADC). The modulator firstly modulates the amplitude of its analog input signal to a multilevel asynchronous duty-cycle modulated signal. Then a time to digital converter (TDC) must be applied to generate digital representation of the received signal from the multi-level asynchronous duty-cycle modulated signal. A multi-level structure has been developed in this work while the prior works often used a single Schmitt. One of the most important limitations in conventional asynchronous... 

As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot... 

New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in class-AB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18μm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method