Sharif Digital Repository

Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise  

Sigma-Delta modulator ADCs used in signal processing applications are usually implemented by switched-capacitor (SC) circuits and CMOS transmission gates. Clock feed-through effect is one of the main non-ideal parameters existing in SC integrators degrading modulator total SNDR and its linearity. In this paper, a comprehensive analysis of clock feed-through effect on CMOS transmission gates on both rising and falling edges on output node will be presented. The main interferer parameters such as clock signal timing model, input signal level and switch parameters effect on output error will be analyzed. Finally, circuit simulations using 0.18um CMOS technology in ADS environment show the... 

The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event transient SET and single event upset SEU, caused by energetic particles striking system wires and flip flops. This paper presents a novel SET/SEU-detection technique for I/O ports where different sampling times used to detect the effects of SET/SEUs. The power dissipation, area, reliability, and propagation delay of the SET/SEU-detection I/O port are analyzed by HSPICE v.X-2005.v9 simulation. The results show that this I/O port can detect all SET/SEUs, by consumption of about 113% more power and occupation of 145% more area than simple I/O port. ©2009 IEEE  

Based on the dynamic criteria for data stability, we introduce segmented virtual grounding architecture with extended read, write noise margin to realize a low leakage current, energy efficient SRAM module. The architecture offers subthreshold operation for the entire module, except for the selected segments. In addition, a new operational mode for the SRAM cell is introduced which allows only the bitlines of the selected columns to be discharged in an operation. The stability of the cells is enhanced in both read and write operation by controlling the cell access time and cell supply voltage, respectively. A 2048$, imes,$20 bit eSRAM unit is implemented in a regular 0.13 $muhbox{m} $ CMOS... 

A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 μW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology. © 2009 IEEE  

A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE  

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during a read/write operation, only selected cell is connected to bit-line when one row is selected whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. Proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS... 

To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM cell using same design rules. Simulation result in standard 0.25μm CMOS technology shows purposed cell has correct operation during read/write and idle mode. The average delay of new cell is 20% smaller than a six-transistor SRAM cell. © 2008 IEEE  

A new low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.18um CMOS technology, with a power supply of 1.4 volt. The results show PSRR is 65dB at 1MHz and the output voltage variation versus temperature (-40 to 140) is less than 0.1%. This circuit shows robustness against process variation. ©2008 IEEE  

A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power... 

A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps... 

This paper presents a new class AB circuit for current-mode signal processing. These current mirrors are especially designed for advanced CMOS technologies and low-voltage high-speed applications. As an example two current amplifiers with a gain of 2, settling time of less than 6ns and current consumption of 500μA are designed and simulated. ©2006 IEEE  

An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS LC oscillator is discussed. The phase noise performance for this kind of oscillator is predicted by using a simplified model. This method enables us to design an optimized oscillator in terms of minimum phase noise and power consumption. The validity of the presented method is demonstrated by designing an LC CMOS oscillator in a 0.24μm CMOS technology. The predictions obtained from the derived expressions are in good agreement with simulation results over a wide range of the supply voltage. © 2004 IEEE  

A high-speed current-mode sample-and-hold circuit is presented. This circuit allows for high sampling speed together with high linearity and precision. The sample-and-hold circuit has been designed and simulated in standard 0.18μm CMOS technology with 1.5V supply voltage. It is capable of operation with sampling frequency of 150MHz (300MHz using double sampling technique) for 12-bit accuracy using 3.7mW power  

A single 1.5 V supply, second order band-pass gm-C filter based on a low-voltage transconductor architecture in standard 0.6 um CMOS process is presented. A dc level shifter circuit (DCLS) is utilized at the input of the proposed transconductor to increase the dc level of the input signal. This makes the input transistors operate in the desired region and hence input voltage swing enhances. DCLS uses a simple voltage doubler as its supply while other parts of the circuit use the main 1.5 V supply. Proposed transconductor shows a THD of -60 dB for 1.4 Vpp,diff input signal with 1 MHz frequency. Also a proper common-mode detector circuit is developed for this low-voltage application. The... 

A 1.8-v 13-bit 25MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.18um CMOS technology. The proposed new high speed low power class AB opamp makes it possible to achieve requirements of 13-bit resolution and settling in 12ns within 0.01% accuracy. An optimum architecture for noise and power consideration is also selected to reduce power. Total Power dissipation is about 82 mw from a single 1.8 v supply, where INL and DNL are 0.7 LSB and 0.6 LSB respectively. SNDR of 75.5 dB is achieved  

A very low power CMOS, 1.5V, 2.5GHz prescaler was designed. Implemented in 0.25u standard CMOS technology, this prescaler can operate up to 3GHz range. The prescaler consists of three delay flip flops (DFF) that work synchronously with RF sinusoidal clock and divides by 4 or 5 according to control signal