Sharif Digital Repository

Different concepts for modelling of soil-foundation in complete dynamic interaction analysis for a 110-m height 70-m span arched structure on 180 piles were investigated in this paper. The modelling approaches consisted of a sophisticated procedure to account for soil compliance and foundation flexibility by defining frequency-dependent springs and dashpots; namely, flexible-impedance base model. The results of this model were compared with those of the conventional modelling procedures; namely, fixed base model and flexible base model by defining frequency-independent springs. In the flexible-impedance base model, the substructure approach was employed through finite element modelling. To... 

Object handling is one of the most important applications of cable-suspended robots, which can be obtained by use of a gripper as its end-effector. In this paper, a novel cable-driven multi-finger gripper assembled on a cable-suspended robot has been presented. Using lock/unlock mechanisms, the under-actuated finger mechanism has been designed to have a human like motion. A cable-suspended robot structure with 3 position degrees of freedom is also proposed by employing active/passive cables in such a way that makes it capable of resisting external moments, while it may be simplified to a spatial point-mass cable robot during positioning operation. Furthermore, the robot workspace has been... 

The application of manipulators is becoming more and more popular in object handling especially when it is desired to have access to remote areas in destructive or hazardous taskspaces. For this purpose, a hand-like mechanism must be designed to be used as an end-effector, which can grasp objects. In this paper a cable driven grasping mechanism has been presented. In the proposed mechanism each finger consists of three phalanxes which are actuated by a single motor. Locking and unlocking constraints are used in the mechanism in order to generate an anthropomorphic motion, in which, the order of reaching phalanxes to the object is sequential. In this way, each phalanx starts moving toward the... 

Design techniques to enhance bandwidth and linearity of broadband multistage low-noise amplifiers (LNAs) are presented. A feedback amplifier circuit is proposed to compensate for transistor gain roll-off with frequency in other amplifier stages and extend overall bandwidth. Moreover, a transistor width tapering in a multistage LNA is applied to improve linearity. These techniques are adopted in a three-stage monolithic microwave integrated circuit (MMIC) LNA implemented in a 0.1-μm GaAs pHEMT process. The LNA features 18-43 GHz bandwidth, 21.6 dB average gain, and 1.8-2.7 noise figure (NF). It exhibits output 1-dB compression point of 11.5 dBm at 30 GHz and consumes 70 mA bias current from a... 

This paper presents a design methodology for class-J monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Theoretical derivations of optimum load impedances, output power, efficiency, and maximum bandwidth are described in presence of nonlinear drain-source resistance of transistors (RDS). A procedure is developed for ideal transistor sizing where transistors are concurrently stabilized and sized to achieve the maximum power-added efficiency (PAE). A 3.5-7 GHz, 0.5-W class-J PA is implemented in a 0.1-μm AlGaAs-InGaAs pHEMT technology to check the accuracy of the proposed approach. With chip dimensions of 1.57 × 1.29 mm2, the PA achieves 56% average PAE over the frequency... 

We introduce a network creation game in which each player (vertex) has a fixed budget to establish links to other players. In this model, each link has a unit price, and each agent tries to minimize its cost, which is either its eccentricity or its total distance to other players in the underlying (undirected) graph of the created network. Two versions of the game are studied: In the MAX version, the cost incurred to a vertex is the maximum distance between the vertex and other vertices, and, in the SUM version, the cost incurred to a vertex is the sum of distances between the vertex and other vertices. We prove that in both versions pure Nash equilibria exist, but the problem of finding the... 

In this paper, we propose a novel method for academic assessment inspired by the decentralized applications made possible by blockchain technology. The proposed method applies to a wide range of academic material, including assignments, exams, academic papers, etc and tackles issues regarding potential personal bias and makes assessment possible without the need to rely on a few assessors. We examine the challenges and possibilities that arise with this method and further explore more general applications in areas such as education. In the experiments conducted for this research, poll results show generally positive views toward the fairness of this system compared to the traditional... 

We are concerned with an open shop scheduling problem having sequence-dependent setup times. A novel bi-objective possibilistic mixed-integer linear programming model is presented. Sequence-dependent setup times, fuzzy processing times and fuzzy due dates with triangular possibility distributions are the main constraints of this model. An open shop scheduling problem with these considerations is close to the real production scheduling conditions. The objective functions are to minimize total weighted tardiness and total weighted completion times. To solve small-sized instances for Pareto-optimal solutions, an interactive fuzzy multi-objective decision making (FMODM) approach, called TH... 

Efficient management of supply chain (SC) requires systematic considerations of miscellaneous issues in its comprehensive version. In this paper, a multi-periodic structure is developed for a supply chain network design (SCND) involving suppliers, factories, distribution centers (DCs), and retailers. The nature of the logistic decisions is tactical that encompasses procurement of raw materials from suppliers, production of finished product at factories, distribution of finished product to retailers via DCs, and the storage of raw materials and end product at factories and DCs. Besides, to make the structure more comprehensive, a flow-shop scheduling model in manufacturing part of the SC is... 

An area and power efficient high-throughput VLSI implementation of a 4 × 4, 64-QAM soft multiple-input-multiple-output (MIMO) detector, that is suitable for high-order constellation schemes is presented. The proposed MIMO detector utilizes information contained in the discarded paths to improve the bit-error-rate (BER) performance, and then reduces computational complexity using three innovative improvement ideas. The proposed design is fabricated and fully tested in a 130 nm CMOS technology. Operating with a 270 MHz clock, the design achieves up to 655 Mbps throughput with 195 mW power dissipation at 1.32 V supply. Synthesis results in 65 nm CMOS technology shows that the proposed... 

A 6-bit passive phase shifter for S frequency band has been designed in a standard HEMT technology. A new switched-network topology has been proposed for implementing the 5.625 phase shift step which these digital bits are series with each other. We used Advanced Design System (ADS2010) to perform simulations. These digital bits will produce 64 different mode phase shift of -177.15 to +177.15 degree. In all cases simulation obtained less than 1 % error  

The reduction of long bone fractures is traditionally an invasive procedure with drawbacks of intense force, soft tissue damage, and, both, rotational and longitudinal malalignment. To combat these drawbacks, we applied a novel, wide open, threelegged, 6-DOF parallel robot, to the current surgical procedure. This platform will balance the accuracy, payload, and workspace for the surgeon, resulting in more efficient, successful surgeries. The experimental tests on a phantom reveal that the mechanism is well capable of applying the desired reduction steps against the large muscular payloads with high accuracy. © 2017 ASME  

The fast growth of battery operated devices has made low power SRAM designs a necessity in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The SRAM performance is limited by the cell stability during different operation. By adding extra transistor to the conventional 6T-cell, hold, read and write static noise margin (SNM) can be improved in the sub-threshold SRAM. In this paper we proposed a new 9T-cell SRAM that shows 80% and 50% improvement in read and write SNM respectively in comparison to the conventional 6T-cell SRAM. Using stack transistors in the leakage current path, the new structure shows lower bitline leakage assisting the sense... 

For the last few decades, phase-noise (PN) improvement of VCOs has been an intriguing problem and remains as one of the challenges in transceiver design. PN in CMOS VCOs, especially close-in PN, greatly suffers from flicker noise. The flicker noise can even degrade the PN at higher offset frequencies (∼1MHz). The close-in PN is important in many communication applications. For instance, IEEE 802.11a/b/g requires a very low PN at 10kHz offset frequency [1] and the PN performance at 100kHz is critical in cellular and Wi-Fi MIMO applications. In addition to the PN performance, oscillators with lower power consumption and smaller area are always on demand  

A low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.25um CMOS technology, with a power supply of 1 volt. The results show PSRR is below -70dB at 1MHz and the output voltage variation versus temperature (0-70) is less than 0.3%. This circuit shows robustness against process variation  

A state-of-the-art low-noise transimpedance amplifier (TIA) for 2.5 Gb/s family is presented using IBM 0.13-m CMOS technology. This TIA would be a part of a homodyne detector in a quantum key distribution (QKD) system. In this work a thorough design methodology based on a novel analytical noise optimization is presented. Also a unique method for eliminating the DC current of the input photodiodes (PDs) is proposed. The post-layout simulation results show bandwidth of 52 kHz to 1.9 GHz, average input referred noise of 1.93 pA/√Hz, and transimpedance gain of 80 db while dissipating 12 mW from a 1.5 V power supply, including the output buffer  

A novel ultra high-throughput detection algorithm with an efficient VLSI architecture for high-order MIMO detectors in the complex constellations is proposed. The main contributions include a new method for the node generation in complex-domain, pipelinable sorters, and a simple combinational circuit instead of the conventional multipliers, which makes the proposed architecture multiplication-free. The proposed design achieves an SNR-independent throughput of 13.3 Gbps at the clock frequency of 556 MHz in a 0.13 μm CMOS technology with a near ML performance. The implemented design consumes 90 pJ per detected bit with the initial latency of 0.3 μs. Also, the synthesis results in a 90 nm CMOS... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at 2f_0 and 3f_0 frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25-μm GaAs pHEMT technology with VDD of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16 transistors in parallel to... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at {2}f {0} and {3}f {0} frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25- μ ext{m} GaAs pHEMT technology with V {DD} of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at {2}f {0} and {3}f {0} frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25- μ ext{m} GaAs pHEMT technology with V {DD} of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16...