Sharif Digital Repository

A pulse-based ultra-wideband transceiver (UWB-IR) operating in the 3.25-4.75 GHz band designed for low power and high data rate communication is implemented in 0.18 μm CMOS technology. When operating at 1 Gbps data rate, it dissipates 98 mW (98 pJ/b) in the receive-mode and 108 mW (108 pJ/b) in the transmit-mode from a 1.8 V supply [1]. Compared to UWB transceivers reported in the literature, this chip dissipates the lowest energy per bit. In addition, the combination of the frequency channelized architecture, high-linearity RF circuits, aggressive baseband filtering, and low local oscillator spurs results in an interference-tolerant receiver that is able to co-exist with systems operating... 

In this paper, we study the effect of non-Poisson traffic patterns on energy consumption for IEEE 802.16e nodes while operating in the sleep mode. In the sleep mode, a Mobile Subscribe Station (MSS) sleeps for a sleep interval and wakes up at the end of this interval in order to check buffered packet(s) at Base Station (BS) destined to it. If there is no packet, the MSS increases the sleep window up to the maximum value and sleeps again. For a more general traffic pattern (rather than Poisson), we evaluate the average power consumption. Based on our analysis, we conclude that traffic pattern plays an important role in power consumption. ©2007 IEEE  

In the sleep mode, a Mobile Subscribe Station (MSS) sleeps for a sleep interval and wakes up at the end of this interval in order to check buffered packet(s) at Base Station (BS) destined to it. If there is no packet, the MSS increases the sleep window up to the maximum value or keeps it unchanged and sleeps again. In this paper, we study the effect of presence of multi service connections with different power saving classes (PSCs) on power consumption for IEEE 802.16e nodes while operating in the sleep mode. Using multi service connections may result in overlapping of availability and unavailability intervals and reducing the effectiveness of power saving mode of the subscriber. © 2007 IEEE... 

NoC is an efficient on-chip communication architecture for SoC architectures. It enables integration of a large number of computational and storage blocks on a single chip. NoCs have tackled the SoCs disadvantages and are scalable. In this paper, we compare two popular NoC topologies, i.e., mesh and torus, in terms of different figures of merit e.g., latency, power consumption, and power/throughput ratio under different routing algorithms and two common traffic models, uniform and hotspot. To the best of our knowledge, this is the first effort in comparing mesh and torus topologies under different routing algorithms and traffic models with respect to their performance and power consumption.... 

The power output of gas turbines (GT) reduces greatly with the increase of the inlet air temperature. This is a serious problem because gas turbines have been used traditionally to provide electricity during the peak power demands, and the peak power demands in many areas occur on summer afternoons. An aquifer thermal energy storage (ATES) was employed for cooling of the inlet air of the GT. Water from a confined aquifer was cooled in winter and was injected back into the aquifer. The stored chilled water was withdrawn in summer to cool the GT inlet air. The heated water was then injected back into the aquifer. A 20 MW GT power plant with 6 and 12 h of operation per day, along with a... 

This paper considers scheduling tasks while minimizing the power consumption of one or more processors, each of which can go to sleep at a fixed cost α. There are two natural versions of this problem, both considered extensively in recent work: minimize the total power consumption (including computation time), or minimize the number of "gaps" in execution. For both versions in a multiprocessor system, we develop a polynomial-time algorithm based on sophisticated dynamic programming. In a generalization of the power-saving problem, where each task can execute in any of a specified set of time intervals, we develop a (1 + 23 α)-approximation, and show that dependence on α is necessary.... 

In this paper, we propose a new SEU-mitigative placement and routing of circuits in the FPGAs which is based on the popular VPR tool. The VPR tool is modified so that during placement and routing, decisions are taken with awareness of SEU-mitigation. Moreover, no redundancies during the placement and routing are used but the algorithms are based on the SEU avoidance. Using the modified tool, i.e., S-VPR, the role of placement and routing algorithms on the fault-tolerance of circuits implemented on FPGAs is achieved. The secondary propose of this paper is to find which of placement or routing is more suited for decreasing SEU sensibility of circuits and to find whether these SEU sensibility... 

Most of the energy efficient routing algorithms proposed for sensor networks are reactive routing algorithms. By definition, reactive algorithms are those in which routes are constructed whenever there is data transmission. In such algorithms, to transmit data packets from a certain transmitter to the corresponding receiver, efficient route will be constructed using RREQ delivery. This delivery is performed via flooding and modified flooding algorithms. One of the most important criteria of such flooding algorithm is not to miss the best final route during RREQ delivery. Most of major algorithms ignored this fact and instead tried to minimize energy consumption during flooding algorithm. But... 

In this report the important factors affecting the levitation melting of nickel are discussed. The relationship between the temperature of a levitated sample to factors such as coil design, gas flow rate, power input, and sample weight are studied. Different coil designs were investigated and compared. It was found that for satisfactory sustained levitation melting, the sample weight, depending on the material, must be within a particular range. Furthermore, increasing the power input would result in a decrease in the droplet temperature; and increasing the weight of the sample results in an increase in the temperature. The flow rate of a cooling gas has a reverse relationship to the... 

Accurate monthly electricity consumption forecasting (ECF) can help retailers enhance the profitability in deregulated electricity markets. Most current methods use monthly load data to perform monthly ECF, which usually produces large errors due to insufficient training samples. A few methods try to use fine-grained smart-meter data (e.g., hourly data) to increase training samples. However, such methods still exhibit low accuracy due to the increase in forecasting steps. © 1975-2012 IEEE  

Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this article, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical... 

This paper proposes two-dimensional directed graphs (or digraphs for short) as a promising alternative to the popular 2D mesh topology for networks-onchip (NoCs). Mesh is the most popular topology for the NoCs, mainly due to its suitability for on-chip implementation and low cost. However, the fact that a digraph offers a lower diameter than its equivalent linear array of equal cost motivated us to evaluate digraphs as the underlying topology of NoCs. This paper introduces a family of NoC topologies based on three well-known digraphs, namely de Bruijn, shuffleexchange, and Kautz. We study topological properties of the proposed topologies. We show that the proposed digraph-based topologies... 

In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require working with decimal numbers while it has been shown that if we convert decimal number to binary ones, this will negatively influence the preciseness required for these applications. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today's digital systems. While the energy consumption of parallel decimal multipliers has not been addressed in previous works, in this paper we present a comparative study of... 

Modern SoC architectures use NoCs for high-speed inter-IP communication. For NoC architectures, high-performance efficient routing algorithms with low power consumption are essential for real-time applications. NoCs with mesh and torus interconnection topologies are now popular due to their simple structures. A torus NoC is very similar to the mesh NoC, but has rather smaller diameter. For a routing algorithm to be deadlock-free in a torus, at least two virtual channels per physical channel must be used to avoid cyclic channel dependencies due to the warp-around links; however, in a mesh network deadlock freedom can be insured using only one virtual channel. The employed number of virtual... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

This paper proposes a power-efficient flow-control method to tackle the problem of crosstalk faults in Network-on-Chips (NoCs). The method, called FRR (Flit Reordering/Rotation), combines three coding mechanisms to entirely eliminate opposite direction transitions (OD transitions) as the source of crosstalk faults in NoC communication channels. The first mechanism, called flit-reordering, reorders flits of every packet to find a flit sequence which produces the lowest number of OD transitions on NoC channels. The second mechanism called flit-rotation, logically rotates the content of every flit of the packet with respect to previously sent flit to achieve even more reduction in the number of... 

In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual...