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    Low-overhead thermally resilient optical network-on-chip architecture

    , Article Nano Communication Networks ; Volume 20 , 2019 , Pages 31-47 ; 18787789 (ISSN) Tinati, M ; Koohi, S ; Hessabi, S ; Sharif University of Technology
    Elsevier B.V  2019
    Abstract
    Integrated silicon photonic networks have attracted a lot of attention in the recent decades due to their potentials for low-power and high-bandwidth communications. However, these promising networks, as the future technology, are drastically susceptible to thermal fluctuations, which may paralyze wavelength-based operation of these networks. In this regard, precise addressing of thermally induced faults in optical networks-on-chip (ONoCs), as well as revealing practical methods to tackle this challenge will be a break-even point toward implementation of this technology. In this paper, thermal variation is investigated through analyzing on-chip power distribution, which is addressed by power... 

    Temperature-aware power consumption modeling in Hyperscale cloud data centers

    , Article Future Generation Computer Systems ; Volume 94 , 2019 , Pages 130-139 ; 0167739X (ISSN) Rezaei Mayahi, M ; Rezazad, M ; Sarbazi Azad, H ; Sharif University of Technology
    Elsevier B.V  2019
    Abstract
    Since the development of data centers, power management (i.e., assessment, consumption and monitoring) has been a great challenge among scientists and engineers. By emerging a new generation of data center in the form of Hyperscale cloud data centers (HCDC), this concern has become more devastating than ever. The huge physical scale and the high level of system utilization through large power compensating system are some of the main characteristics of today's HCDC. The lack of appropriate power assessment from available power estimation models, prevents professionals from designing an accurate HCDCcapacity planning. In particular, during steady state workload processing at the high... 

    A prediction-based and power-aware virtual machine allocation algorithm in three-tier cloud data centers

    , Article International Journal of Communication Systems ; Volume 32, Issue 3 , 2019 ; 10745351 (ISSN) Tarahomi, M ; Izadi, M ; Sharif University of Technology
    John Wiley and Sons Ltd  2019
    Abstract
    With the increasing popularity of cloud computing services, the more number of cloud data centers are constructed over the globe. This makes the power consumption of cloud data center elements as a big challenge. Hereby, several software and hardware approaches have been proposed to handle this issue. However, this problem has not been optimally solved yet. In this paper, we propose an online cloud resource management with live migration of virtual machines (VMs) to reduce power consumption. To do so, a prediction-based and power-aware virtual machine allocation algorithm is proposed. Also, we present a three-tier framework for energy-efficient resource management in cloud data centers.... 

    Peak power management to meet thermal design power in fault-tolerant embedded systems

    , Article IEEE Transactions on Parallel and Distributed Systems ; Volume 30, Issue 1 , 2019 , Pages 161-173 ; 10459219 (ISSN) Ansari, M ; Safari, S ; Yeganeh Khaksar, A ; Salehi, M ; Ejlali, A. R ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    Multicore platforms provide a great opportunity for implementation of fault-tolerance techniques to achieve high reliability in real-time embedded systems. Passive redundancy is well-suited for multicore platforms and a well-established technique to tolerate transient and permanent faults. However, it incurs significant power overheads, which go wasted in fault-free execution scenarios. Meanwhile, due to the Thermal Design Power (TDP) constraint, in some cases, it is not feasible to simultaneously power on all cores on a multicore platform. Since TDP is the maximum sustainable power that a chip can consume, violating TDP makes some cores automatically restart or significantly reduce their... 

    Providing RS participation for geo-distributed data centers using deep learning-based power prediction

    , Article 2nd International Congress on High-Performance Computing and Big Data Analysis, TopHPC 2019, 23 April 2019 through 25 April 2019 ; Volume 891 , 2019 , Pages 3-17 ; 18650929 (ISSN); 9783030334949 (ISBN) Taheri, S ; Goudarzi, M ; Yoshie, O ; Sharif University of Technology
    Springer  2019
    Abstract
    Nowadays, geo-distributed Data Centers (DCs) are very common, because of providing more energy efficiency, higher system availability as well as flexibility. In a geo-distributed cloud, each local DC responds to the specific portion of the incoming load which distributed based on different Geographically Load Balancing (GLB) policies. As a large yet flexible power consumer, the local DC has a great impact on the local power grid. From this point of view, a local DC is a good candidate to participate in the emerging power market such as Regulation Service (RS) opportunity, that brings monetary benefits both for the DC as well as the grid. However, a fruitful collaboration requires the DC to... 

    Peak power management to meet thermal design power in fault-tolerant embedded systems

    , Article IEEE Transactions on Parallel and Distributed Systems ; Volume 30, Issue 1 , 2019 , Pages 161-173 ; 10459219 (ISSN) Ansari, M ; Safari, S ; Yeganeh Khaksar, A ; Salehi, M ; Ejlali, A ; Sharif University of Technology
    IEEE Computer Society  2019
    Abstract
    Multicore platforms provide a great opportunity for implementation of fault-tolerance techniques to achieve high reliability in real-time embedded systems. Passive redundancy is well-suited for multicore platforms and a well-established technique to tolerate transient and permanent faults. However, it incurs significant power overheads, which go wasted in fault-free execution scenarios. Meanwhile, due to the Thermal Design Power (TDP) constraint, in some cases, it is not feasible to simultaneously power on all cores on a multicore platform. Since TDP is the maximum sustainable power that a chip can consume, violating TDP makes some cores automatically restart or significantly reduce their... 

    Providing RS participation for geo-distributed data centers using deep learning-based power prediction

    , Article 2nd International Congress on High-Performance Computing and Big Data Analysis, TopHPC 2019, 23 April 2019 through 25 April 2019 ; Volume 891 , 2019 , Pages 3-17 ; 18650929 (ISSN) ; 9783030334949 (ISBN) Taheri, S ; Goudarzi, M ; Yoshie, O ; Sharif University of Technology
    Springer  2019
    Abstract
    Nowadays, geo-distributed Data Centers (DCs) are very common, because of providing more energy efficiency, higher system availability as well as flexibility. In a geo-distributed cloud, each local DC responds to the specific portion of the incoming load which distributed based on different Geographically Load Balancing (GLB) policies. As a large yet flexible power consumer, the local DC has a great impact on the local power grid. From this point of view, a local DC is a good candidate to participate in the emerging power market such as Regulation Service (RS) opportunity, that brings monetary benefits both for the DC as well as the grid. However, a fruitful collaboration requires the DC to... 

    An efficient SRAM-Based reconfigurable architecture for embedded processors

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 38, Issue 3 , 2019 , Pages 466-479 ; 02780070 (ISSN) Tamimi, S ; Ebrahimi, Z ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    Nowadays, embedded processors are widely used in wide range of domains from low-power to safety-critical applications. By providing prominent features such as variant peripheral support and flexibility to partial or major design modifications, field-programmable gate arrays (FPGAs) are commonly used to implement either an entire embedded system or a hardware description language-based processor, known as soft-core processor. FPGA-based designs, however, suffer from high power consumption, large die area, and low performance that hinders common use of soft-core processors in low-power embedded systems. In this paper, we present an efficient reconfigurable architecture to implement soft-core... 

    Energy-efficient service provisioning in inter-data center elastic optical networks

    , Article IEEE Transactions on Green Communications and Networking ; Volume 3, Issue 1 , 2019 , Pages 180-191 ; 24732400 (ISSN) Hadi, M ; Pakravan, M. R ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    We investigate the problem of energy-efficient transponder configuration constrained to quality of service and physical requirements in orthogonal frequency division multiplexing-based software-defined inter-data center elastic optical networks. We consider two types of services which are called delay-sensitive and delay-Tolerant. A deterministic and a stochastic mixed-integer nonlinear program with a target of minimizing the total transponder power consumption are formulated which their solutions provide a long-Term and a short-Term configuration for delay-sensitive service and delay-Tolerant service transponders, respectively. We use geometric and stochastic Lyapunov optimization... 

    Peak-power-aware energy management for periodic real-time applications

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 39, Issue 4 , 2020 , Pages 779-788 Ansari, M ; Yeganeh Khaksar, A ; Safari, S ; Ejlali, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Two main objectives in designing real-time embedded systems are high reliability and low power consumption. Hardware replication (e.g., standby-sparing) can provide high reliability while keeping the power consumption under control. In this paper, we consider a standby-sparing system where the main tasks on primary cores are scheduled by our proposed peak-power-aware earliest-deadline-first policy while the backup tasks on spare cores are scheduled by our proposed peak-power-aware earliest-deadline-late policy to meet the chip thermal design power (TDP) constraint. These policies provide the best opportunity to shift the task executions as much as possible to minimize execution overlaps... 

    Meeting thermal safe power in fault-tolerant heterogeneous embedded systems

    , Article IEEE Embedded Systems Letters ; Volume 12, Issue 1 , 2020 , Pages 29-32 Ansari, M ; Pasandideh, M ; Saber Latibari, J ; Ejlali, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Due to the system-level power constraints, it is encountered that not all cores in a multicore chip can be simultaneously powered-on at the highest voltage/frequency levels. Also, in the future technology nodes, reliability issues due to the susceptibility of systems to transient faults should be considered in multicore platforms. Therefore, two major objectives in designing multicore embedded systems are low energy/power consumption and high reliability. This letter presents an energy management system that optimizes the energy consumption such that it satisfies reliability target and meets timing, thermal design power (TDP) and thermal safe power (TSP) constraints. Toward the... 

    Joint optimization of power consumption and transmission delay in a cache-enabled C-RAN

    , Article IEEE Wireless Communications Letters ; Volume 9, Issue 8 , 2020 , Pages 1137-1140 Abdollahi Bafghi, A. H ; Mirmohseni, M ; Ashtiani, F ; Nasiri Kenari, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    In this letter, we consider a cache-enabled cloud radio access network with single-antenna base stations and single-antenna mobile users. Each base station can access the central processor of the network via a separate backhaul link with limited capacity. We utilize the interference alignment scheme as the transmission strategy between base stations and users. By assuming a block transmission scheme, we define a related data transmission delay. We derive the transmission delay and network power consumption. At last, we solve the problem of joint optimization of data transmission delay and network power consumption using DC programming algorithm. In our numerical results, we investigate the... 

    Low power receiver with merged N-path LNA and mixer for MICS applications

    , Article AEU - International Journal of Electronics and Communications ; Volume 117 , 2020 Beigi, A ; Safarian, A ; Sharif University of Technology
    Elsevier GmbH  2020
    Abstract
    In this paper, a low power receiver for medical implant communication service (MICS) is presented. Low power design is vital in the MICS applications since the implanted chip has to work for a long time without the need to change its battery. As a result, a merged N-path low noise amplifier (LNA) and mixer block is proposed. In this structure, the LNA and down-conversion mixer share a transconductance to lower the overall power consumption. An N-path feedback is utilized around the shared transconductance not only to improve the LNA selectivity and relax the linearity requirements but also to downconvert the radio frequency (RF) component and create the intermediate frequency (IF) signal. In... 

    A low-power signal-dependent sampling technique: analysis, implementation, and applications

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 67, Issue 12 , 2020 , Pages 4334-4347 Hadizadeh Hafshejani, E ; Elmi, M ; Taherinejad, N ; Fotowat Ahmady, A ; Mirabbasi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Sensors are among essential building blocks of any Cyber-Physical Systems (CPSs). Acquisition and processing of their sensory data contribute to the power consumption and computation load of the overall CPSs. For data acquisition, the conventional fixed frequency sampling in many such systems is sub-optimal since a sizable number of samples do not contain important information. In this work, we propose a Signal-Dependent Sampling (SDS) method and present its associated circuit implementation. Using the proposed SDS method, the number of retained samples is significantly reduced with little or negligible compromise in the quality of the (reconstructed) signal. The associated error and added... 

    Power-Aware run-time scheduler for mixed-criticality systems on multi-core platform

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; 2020 Ranjbar, B ; Nguyen, T. D. A ; Ejlali, A ; Kumar, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    In modern multi-core Mixed-Criticality (MC) systems, a rise in peak power consumption due to parallel execution of tasks with maximum frequency, specially in the overload situation, may lead to thermal issues, which may affect the reliability and timeliness of MC systems. Therefore, managing peak power consumption has become imperative in multi-core MC systems. In this regard, we propose an online peak power and thermal management heuristic for multi-core MC systems. This heuristic reduces the peak power consumption of the system as much as possible during runtime by exploiting dynamic slack and per-cluster Dynamic Voltage and Frequency Scaling (DVFS). Specifically, our approach examines... 

    Yield constrained automated design algorithm for power optimized pipeline ADC

    , Article Integration ; Volume 74 , 2020 , Pages 55-62 Sadrafshari, V ; Sadrafshari, S ; Sharifkhani, M ; Sharif University of Technology
    Elsevier B.V  2020
    Abstract
    Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit... 

    An efficient power-aware VM allocation mechanism in cloud data centers: a micro genetic-based approach

    , Article Cluster Computing ; 2020 Tarahomi, M ; Izadi, M ; Ghobaei Arani, M ; Sharif University of Technology
    Springer  2020
    Abstract
    Efficiency in cloud servers’ power consumption is of paramount importance. Power efficiency makes the reduction in greenhouse gases establishing the concept of green computing. One of the beneficial ways is to apply power-aware methods to decide where to allocate virtual machines (VMs) in data center physical resources. Virtualization is utilized as a promising technology for power-aware VM allocation methods. Since the VM allocation is an NP-complete problem, we use of evolutionary algorithms to solve it. This paper presents an effective micro-genetic algorithm in order to choose suitable destinations between physical hosts for VMs. Our evaluations in simulation environment show that... 

    Ring- DVFS: reliability-aware reinforcement learning-based DVFS for real-time embedded systems

    , Article IEEE Embedded Systems Letters ; October , 2020 , Page:1-1 Yeganeh Khaksar, A ; Ansari, M ; Safari, S ; Yari Karin, S ; Ejlali, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Dynamic Voltage and Frequency Scaling (DVFS) is one of the most popular and exploited techniques to reduce power consumption in multicore embedded systems. However, this technique might lead to a task-reliability degradation because scaling the voltage and frequency increases the fault rate and the worst-case execution time of the tasks. In order to preserve taskreliability at an acceptable level as well as achieving power saving, in this letter, we have proposed an enhanced DVFS method based on reinforcement learning to reduce the power consumption of sporadic tasks at runtime in multicore embedded systems without task-reliability degradation. The reinforcement learner takes decisions based... 

    ReMap: reliability management of peak-power-aware real-time embedded systems through task replication

    , Article IEEE Transactions on Emerging Topics in Computing ; August , 2020 , Pages: 1-1 Yeganeh Khaksar, A ; Ansari, M ; Ejlali, A ; Sharif University of Technology
    IEEE Computer Society  2020
    Abstract
    Increasing power densities in future technology nodes is a crucial issue in multicore platforms. As the number of cores increases in them, power budget constraints may prevent powering all cores simultaneously at full performance level. Therefore, chip manufacturers introduce a power budget constraint as Thermal Design Power (TDP) for chips. Meanwhile, multicore platforms are suitable for implementation of fault-tolerance techniques to achieve high reliability. Task Replication is a known technique to tolerate transient faults. However, careless task replication may lead to significant peak power consumption. In this paper, we consider the problem of achieving a given reliability target... 

    A power efficient approach to fault-tolerant register file design

    , Article Proceedings of the IEEE International Frequency Control Symposium and Exposition, 4 January 2008 through 8 January 2008, Hyderabad ; 2008 , Pages 21-26 ; 0769530834 (ISBN); 9780769530833 (ISBN) Amiri Kamalabad, M ; Miremadi, S. G ; Fazeli, M ; Sharif University of Technology
    2008
    Abstract
    Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: Single Error Correction (SEC) hamming code, duplication with parity, and Triple Modular Redundancy (TMR). As a case study, this approach is implemented on the register file of an...