Sharif Digital Repository

The aim of this paper is developing a new hierarchical model to evaluate and rank the sawability (power consumption) of carbonate rock with the use of effective and major criteria, and simultaneously taking subjective judgments of decision makers into consideration. The proposed approach is based on the combination of Fuzzy Analytic Hierarchy Process (FAHP) method with TOPSIS (Technique for Order Preference by Similarity to Ideal Solution) methods. FAHP is used for determining the weights of the criteria by decision makers, and then rankings of carbonate rocks are determined by TOPSIS. The proposed method is applied for Iranian ornamental stone to evaluate the power consumption in rock... 

In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

Aggregating fine-granular data measurements from smart meters presents an opportunity for utility companies to learn about consumers' power consumption patterns. Several research studies have shown that power consumption patterns can reveal a range of information about consumers, such as how many people are in the home, the types of appliances they use, their eating and sleeping routines, and even the TV programs they watch. As we move toward liberalized energy markets, many different parties are interested in gaining access to such data, which has enormous economical, societal, and environmental benefits. However, the main concern is that many such beneficial uses of smart meter big data... 

In this paper, we present an energy-efficient manycast routing and spectrum assignment (EEM-RSA) algorithm in elastic optical networks supporting cloud computing applications. The proposed EEM-RSA is adapted for both static and dynamic scenarios. First, an integer linear programing formulation is derived for energy-efficient manycasting and spectrum assignment; then, the corresponding heuristic methods are proposed. To reduce the energy consumption, inactive (idle) elements are turned off, and in the proposed energy-efficient manycasting heuristic, the number of activated elements are minimized. The power consumption of network elements is modeled by considering a constant overhead for the... 

Network-on-Chip (NoC) is a key element in the total power consumption of a chip multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs since it contributes to reduction in both static and dynamic power consumptions. In this paper, we propose a novel scheme to reduce on-chip network power consumption when the number of Virtual Channels (VCs) with active allocation requests per cycle is less than the number of total VCs. In our method, we introduce a reconfigurable arbitration logic which can be configured to have multiple latencies and hence, multiple slack times. The increased slack times are then used to reduce the supply voltage of the routers in order to... 

Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system for many-core processors. It exploits various basic redundancy techniques (like, dual and triple modular redundancy) operating in different voltage-frequency levels, each offering distinct reliability, performance and power properties. Our system performs Dynamic Redundancy and Voltage Scaling... 

Owing to wind power inherent characteristics and technical constraints of power systems operation, a considerable amount of wind energy cannot be delivered to load centers and gets curtailed. Transmission congestion together with temporal mismatch between load and available wind power can be accounted as the main reasons for this unpleasant event. This paper aims to concentrate on the wind energy curtailment for which it provides a combinatorial planning model to maximize wind power utilization. Jointly operating the wind power generation system with pumped hydro energy storage (PHES), the planning procedure tries to reach schemes with the minimum level of wind energy curtailment as well as... 

The reliable transfer in Network on Chips (NoCs) can be threatened by crosstalk fault occurring in wires. Crossstalk fault is due to inter-wire coupling capacitance that based on the patterns of transitions appearing on the wires, significantly limits the reliability of NoCs. Among these transitions, 101 and 010 bit patterns impose the worst crosstalk effects to wires. This work intends to increase the reliability of NoCs against crosstalk faults by applying an improved Fibonacci-based numeral system, called Doubled-Penultimate Fibonacci (DP-Fibo). In the DP-Fibo coding algorithm, code words without ‘101’ and ‘010’ bit patterns are produced to reduce crosstalk faults. Experimental results... 

High reliability and low power consumption are among the major requirements in design of wireless sensor networks (WSNs). In this paper, a multi-objective problem is formulated as a Joint Power consumption and data Reliability (JPR) optimization problem. For this purpose, a connected dominating set (CDS)-based topology control approach is proposed. Our objective is to self-organize the network with minimum interference and power consumption. We consider the power changes into a topology with minimum CDS infrastructure subject to connectivity constraints. Since this problem is NP-hard, it cannot be dealt with using polynomial-time exact algorithms. Therefore, we first present a genetic... 

End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual... 

A task migration scheme for homogeneous chip multiprocessors (CMP) is presented in this paper. The proposed migration mechanism focuses on the communication sub-system and aims to reduce the total power consumption and latency of the network-on-chip (NoC). In this work, starting from an initial mapping, the tasks migrate to new cores in such a way that the distance between the end-point nodes of high-volume communication flows is reduced. Finding the new place for a task is done in a distributed manner by applying an iterative local search that relies on the local information of each task about its communication demand. The task migration procedure also includes a pre-migration step that... 

Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on... 

In this paper, we study the power allocation problem in multi-cell OFDMA networks, where given the tradeoff between user satisfaction and profit of the service provider, maximizing the revenue of the service provider is also taken into account. Consequently, two Stackelberg games are proposed for allocating proper powers to central and cell-edge users. In our algorithm, assuming the fact that users agree to pay more for better QoS level, the service provider imposes optimum prices for unit-power transmitted to users as they request different levels of QoS. In addition, in order to improve system performance at cell-edge locations, users are divided into two groups based on their distance to... 

In this paper we propose a new method for applying hiding countermeasure against CPA attacks. This method is for software implementation, based on smoothing power consumption of the device. We propose a new heuristic encoding scheme for implementing block cipher algorithms. Our new method includes only AND-equivalent and XOR-equivalent operations since every cryptographic algorithm can be implemented with two basic operations, namely AND, XOR. In order to practically evaluate resistance improvement against CPA, we implement the proposed coding scheme on SIMON, a lightweight block cipher, on a smartcard with ATmega163 microprocessor. The results of this implementation show a 350 times more... 

Accurate prediction of electricity demand is essential for planning, policy making and resource allocation in national level. In this manuscript, we applied a number of artificial intelligence methods to predict macro-scale electricity consumption rates in Iran. To this end, three socio-economic and three environmental factors were considered as inputs to the prediction models. We used data for the period 1967-2013 in order to predict the power demand in the years 2014-2018. Experimental results showed that the path coefficient analysis model with linear coefficients had the best performance among the models considered in this study. The outcome of this research can help the policy makers to... 

Network on chip (NoC) has been proposed as an appropriate solution for today’s on-chip communication challenges. Power dissipation has become a key factor in the NoCs because of their shrinking sizes. In this paper, we propose a new encoding approach aimed at power reduction by decreasing the number of switching activities on the buses. This approach assigns the symbols to data word in such a way that the more frequent words are sent by less power consumption. This algorithm dedicates the symbols with less ones to high probability data and uses transition signaling to transmit data. The proposed method, unlike the existing low power encoding, does not rely on spatial redundancy and keeps the... 

Inter-wire coupling capacitances can lead to crosstalk fault that is strongly dependent on the transition patterns appearing on the wires. These transition patterns can cause mutual influences between adjacent wires of NoCs and as a result threaten the reliability of data transfer seriously. To increase the reliability of NoCs against the crosstalk fault, Forbidden Pattern Free (FPFs) codes are used. To generate FPF codes, numerical systems are among the overhead-efficient mechanisms. The algorithms of numerical systems have direct effect on the amounts of the codec overheads including power consumption, area occupation and performance of NoCs. To find an overhead-efficient numerical system,... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, PMOS transistors are used at the input of the first and second stages of the comparator. At the evaluation phase, the second stage is activated after the first stage with a predetermined delay to achieve a controllable pre-amplifier gain. Also, the first stage is turned off after the delay to reduce overall power consumption. Simulation results in 0.18 μτη CMOS technology, prove that the proposed circuit reduces the power consumption by a factor of two and reduces comparison time as large as 210ps in the same budget of offset voltage compared to the conventional circuit. Moreover, the offset voltage and power... 

Refrigerators have considerable share of residential consumption. They can be, however, flexible loads because their operating time and consumption patterns can be changed to some extent. Accordingly, they can be selected as a target for the study of Demand Side Management plans. In this paper, two experimental models for a refrigerator are derived. In obtaining the first model, following assumptions are made: the ambient temperature of refrigerator is assumed to be constant and the refrigerator door is remained closed. However, in the second model the variation of ambient temperature and door-opening effects are considered according to some general patterns. Further, two strategies are... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing...